Subversion Repositories tinyvliw8

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2011 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II

# Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition

# Date created = 15:41:59  February 24, 2014

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               AlteraDK1_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone II"

set_global_assignment -name DEVICE EP2C20F484C7

set_global_assignment -name TOP_LEVEL_ENTITY AlteraDK1

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.0 SP1"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:59  FEBRUARY 24, 2014"

set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"

set_location_assignment PIN_D12 -to clock

set_location_assignment PIN_E2 -to hex0[6]

set_location_assignment PIN_F1 -to hex0[5]

set_location_assignment PIN_F2 -to hex0[4]

set_location_assignment PIN_H1 -to hex0[3]

set_location_assignment PIN_H2 -to hex0[2]

set_location_assignment PIN_J1 -to hex0[1]

set_location_assignment PIN_J2 -to hex0[0]

set_location_assignment PIN_D1 -to hex1[6]

set_location_assignment PIN_D2 -to hex1[5]

set_location_assignment PIN_G3 -to hex1[4]

set_location_assignment PIN_H4 -to hex1[3]

set_location_assignment PIN_H5 -to hex1[2]

set_location_assignment PIN_H6 -to hex1[1]

set_location_assignment PIN_E1 -to hex1[0]

set_location_assignment PIN_D3 -to hex2[6]

set_location_assignment PIN_E4 -to hex2[5]

set_location_assignment PIN_E3 -to hex2[4]

set_location_assignment PIN_C1 -to hex2[3]

set_location_assignment PIN_C2 -to hex2[2]

set_location_assignment PIN_G6 -to hex2[1]

set_location_assignment PIN_G5 -to hex2[0]

set_location_assignment PIN_D4 -to hex3[6]

set_location_assignment PIN_F3 -to hex3[5]

set_location_assignment PIN_L8 -to hex3[4]

set_location_assignment PIN_J4 -to hex3[3]

set_location_assignment PIN_D6 -to hex3[2]

set_location_assignment PIN_D5 -to hex3[1]

set_location_assignment PIN_F4 -to hex3[0]

set_location_assignment PIN_A13 -to jp1[0]

set_location_assignment PIN_B13 -to jp1[1]

set_location_assignment PIN_A14 -to jp1[2]

set_location_assignment PIN_B14 -to jp1[3]

set_location_assignment PIN_A15 -to jp1[4]

set_location_assignment PIN_B15 -to jp1[5]

set_location_assignment PIN_A16 -to jp1[6]

set_location_assignment PIN_B16 -to jp1[7]

set_location_assignment PIN_A17 -to jp1[8]

set_location_assignment PIN_B17 -to jp1[9]

set_location_assignment PIN_A18 -to jp1[10]

set_location_assignment PIN_B18 -to jp1[11]

set_location_assignment PIN_A19 -to jp1[12]

set_location_assignment PIN_B19 -to jp1[13]

set_location_assignment PIN_A20 -to jp1[14]

set_location_assignment PIN_B20 -to jp1[15]

set_location_assignment PIN_C21 -to jp1[16]

set_location_assignment PIN_C22 -to jp1[17]

set_location_assignment PIN_D21 -to jp1[18]

set_location_assignment PIN_D22 -to jp1[19]

set_location_assignment PIN_E21 -to jp1[20]

set_location_assignment PIN_E22 -to jp1[21]

set_location_assignment PIN_F21 -to jp1[22]

set_location_assignment PIN_F22 -to jp1[23]

set_location_assignment PIN_G21 -to jp1[24]

set_location_assignment PIN_G22 -to jp1[25]

set_location_assignment PIN_J21 -to jp1[26]

set_location_assignment PIN_J22 -to jp1[27]

set_location_assignment PIN_K21 -to jp1[28]

set_location_assignment PIN_K22 -to jp1[29]

set_location_assignment PIN_J19 -to jp1[30]

set_location_assignment PIN_J20 -to jp1[31]

set_location_assignment PIN_J18 -to jp1[32]

set_location_assignment PIN_K20 -to jp1[33]

set_location_assignment PIN_L19 -to jp1[34]

set_location_assignment PIN_L18 -to jp1[35]

set_location_assignment PIN_H12 -to jp2[0]

set_location_assignment PIN_H13 -to jp2[1]

set_location_assignment PIN_H14 -to jp2[2]

set_location_assignment PIN_G15 -to jp2[3]

set_location_assignment PIN_E14 -to jp2[4]

set_location_assignment PIN_E15 -to jp2[5]

set_location_assignment PIN_F15 -to jp2[6]

set_location_assignment PIN_G16 -to jp2[7]

set_location_assignment PIN_F12 -to jp2[8]

set_location_assignment PIN_F13 -to jp2[9]

set_location_assignment PIN_C14 -to jp2[10]

set_location_assignment PIN_D14 -to jp2[11]

set_location_assignment PIN_D15 -to jp2[12]

set_location_assignment PIN_D16 -to jp2[13]

set_location_assignment PIN_C17 -to jp2[14]

set_location_assignment PIN_C18 -to jp2[15]

set_location_assignment PIN_C19 -to jp2[16]

set_location_assignment PIN_C20 -to jp2[17]

set_location_assignment PIN_D19 -to jp2[18]

set_location_assignment PIN_D20 -to jp2[19]

set_location_assignment PIN_E20 -to jp2[20]

set_location_assignment PIN_F20 -to jp2[21]

set_location_assignment PIN_E19 -to jp2[22]

set_location_assignment PIN_E18 -to jp2[23]

set_location_assignment PIN_G20 -to jp2[24]

set_location_assignment PIN_G18 -to jp2[25]

set_location_assignment PIN_G17 -to jp2[26]

set_location_assignment PIN_H17 -to jp2[27]

set_location_assignment PIN_J15 -to jp2[28]

set_location_assignment PIN_H18 -to jp2[29]

set_location_assignment PIN_N22 -to jp2[30]

set_location_assignment PIN_N21 -to jp2[31]

set_location_assignment PIN_P15 -to jp2[32]

set_location_assignment PIN_N15 -to jp2[33]

set_location_assignment PIN_P17 -to jp2[34]

set_location_assignment PIN_P18 -to jp2[35]

set_location_assignment PIN_T21 -to key[3]

set_location_assignment PIN_T22 -to key[2]

set_location_assignment PIN_R21 -to key[1]

set_location_assignment PIN_R22 -to key[0]

set_location_assignment PIN_Y21 -to led_green[7]

set_location_assignment PIN_Y22 -to led_green[6]

set_location_assignment PIN_W21 -to led_green[5]

set_location_assignment PIN_W22 -to led_green[4]

set_location_assignment PIN_V21 -to led_green[3]

set_location_assignment PIN_V22 -to led_green[2]

set_location_assignment PIN_U21 -to led_green[1]

set_location_assignment PIN_U22 -to led_green[0]

set_location_assignment PIN_R17 -to led_red[9]

set_location_assignment PIN_R18 -to led_red[8]

set_location_assignment PIN_U18 -to led_red[7]

set_location_assignment PIN_Y18 -to led_red[6]

set_location_assignment PIN_V19 -to led_red[5]

set_location_assignment PIN_T18 -to led_red[4]

set_location_assignment PIN_Y19 -to led_red[3]

set_location_assignment PIN_U19 -to led_red[2]

set_location_assignment PIN_R19 -to led_red[1]

set_location_assignment PIN_R20 -to led_red[0]

set_location_assignment PIN_L2 -to sw[9]

set_location_assignment PIN_M1 -to sw[8]

set_location_assignment PIN_M2 -to sw[7]

set_location_assignment PIN_U11 -to sw[6]

set_location_assignment PIN_U12 -to sw[5]

set_location_assignment PIN_W12 -to sw[4]

set_location_assignment PIN_V12 -to sw[3]

set_location_assignment PIN_M22 -to sw[2]

set_location_assignment PIN_L21 -to sw[1]

set_location_assignment PIN_L22 -to sw[0]

set_location_assignment PIN_F14 -to uart0_rxd

set_location_assignment PIN_G12 -to uart0_txd

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7

set_global_assignment -name VHDL_FILE AlteraDK1.vhd

set_global_assignment -name QIP_FILE dataMem.qip

set_global_assignment -name QIP_FILE instMem.qip

set_global_assignment -name SDC_FILE AlteraDK1.sdc

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/vliwProc.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/statusReg.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/regSet.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/pcReg.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/loadStore.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/jmpExec.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/irqCntl.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/instDecoder.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/alu.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/library/latch.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/timer.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/spiSlave.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/spiMaster.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/rstCtrl.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/ioport.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/gendelay.vhd

set_global_assignment -name VHDL_FILE ../../src/vhdl/clock_divider.vhd

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top