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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [ioport.vhd] - Blame information for rev 10

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-- ************************************************************************
-- * This is a RTL Model of the MSP430 IO ports without interrupt 
-- * functionality
-- *
-- * This io-port fits the behavior of the msp430 io-port. The functionality 
-- * of the in- and output lines(the output value is also written to the 
-- * input) is provided by the sgb25v io-pads
-- *
-- * author: g.panic - IHP, date: 2011-02-07
-- * version: 1.1
-- *
-- * Revision:
-- * changed clock behavior, clock used only in connection with mdbwr_n 
-- *
-- ************************************************************************
 
library ieee;
use ieee.std_logic_1164.all;
 
ENTITY ioport IS
        PORT (
                cs_n     : IN  STD_LOGIC;                                   -- chip select signal
 
                        clk      : IN  STD_LOGIC;
 
                        -- memory interface
                mdbwr_n  : IN  STD_LOGIC;                    -- write enable signal    
                mdb_i           : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus
                mdb_o           : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus    
                mab     : IN  STD_LOGIC_VECTOR(2 downto 0);      -- address registers 
 
                        -- interrupt interface
                        irq      : out std_logic;
                        irqAck   : in std_logic;
 
                -- port interface
                PnIN    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
                PnOUT           : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
                PnOEN   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
 
                rst_n           : IN STD_LOGIC
                );
END ioport;
 
ARCHITECTURE beh OF ioport IS
 
        SIGNAL PxIN  : STD_LOGIC_VECTOR(7 DOWNTO 0);
        SIGNAL PxOUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
        SIGNAL PxDIR : STD_LOGIC_VECTOR(7 DOWNTO 0);
        SIGNAL PxSEL : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
        SIGNAL PxIES : STD_LOGIC_VECTOR(7 DOWNTO 0);
        SIGNAL PxIE  : STD_LOGIC_VECTOR(7 DOWNTO 0);
        SIGNAL PxIFG : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
        SIGNAL IRQ_S : STD_LOGIC;
        SIGNAL CLK_S : STD_LOGIC;
 
        SIGNAL ifg_clk : std_logic_vector(7 downto 0);
        SIGNAL int     : std_logic_vector(7 downto 0);
 
BEGIN
 
        CLK_S <= clk;
 
-------------------------------------------------------------------------------------
-- INTERRUPTS
-------------------------------------------------------------------------------------
 
        int_edge_gen: for i in 0 to 7 generate
        begin
                process (PxIN(i), PxSEL(i), PxIES(i))
                begin
                        if PxSEL(i) = '0' then
                                if PxIES(i) = '0' then
                                        int(i) <= PxIN(i);
                                else
                                        int(i) <= not(PxIN(i));
                                end if;
                        else
                                int(i) <= '0';
                        end if;
                end process;
        end generate;
 
        -- generate access clocks to PxIFG, CPU acces has priority
        ifg_clk_gen: for i in 0 to 7 generate
        begin
                ifg_clk(i) <= not(mdbwr_n) when (cs_n = '0' and mab = "110") else int(i);
        end generate;
 
        -- write PxIFG
        PxIFG_gen: for i in 0 to 7 generate
        begin
        write_ifg : PROCESS (rst_n, ifg_clk(i))
        BEGIN
                IF rst_n = '0' THEN
                        PxIFG(i) <= '0';
                ELSE
                   IF (ifg_clk(i)'event and ifg_clk(i) = '1') THEN
                                IF cs_n = '0' and mab = "110" THEN
                                        IF mdbwr_n = '0' THEN
                                                PxIFG(i) <= PxIFG(i) and not(mdb_i(i));
                                        END IF;
                                ELSE
                                        PxIFG (i) <= '1';
                                END IF;
                        END IF;
                END IF;
        END PROCESS;
        end generate;
 
-------------------------------------------------------------------------------------
-- REGISTERS
-------------------------------------------------------------------------------------
 
 
        -------------------------------------------------------------------------------------
        -- write registers
        -------------------------------------------------------------------------------------
 
        -- PxDIR
        write_l_proc : PROCESS(rst_n, mdbwr_n)
        BEGIN
                IF rst_n = '0' THEN
                        PxDIR <= (OTHERS => '0');
                        PxOUT <= (OTHERS => '0');
                        PxSEL <= (OTHERS => '0');
                        PxIES <= (OTHERS => '0');
                        PxIE  <= (OTHERS => '0');
                ELSE
                        if (mdbwr_n'event and mdbwr_n = '0') then
                                IF cs_n = '0' THEN
                                        CASE mab IS
                                                WHEN "000" => PxDIR <= mdb_i;
                                                WHEN "001" => PxOUT <= mdb_i;
                                                WHEN "011" => PxSEL <= mdb_i;
                                                WHEN "100" => PxIES <= mdb_i;
                                                WHEN "101" => PxIE <= mdb_i;
                                                WHEN others => null;
                                        END CASE;
                                end if;
                        end if;
                END IF;
        END PROCESS;
 
        -------------------------------------------------------------------------------------
        -- read registers
        -------------------------------------------------------------------------------------
 
        mdb_o <= PxDIR when cs_n = '0' and mab = "000" else
                 PxOUT when cs_n = '0' and mab = "001" else
                                PxIN  when cs_n = '0' and mab = "010" else
                                PxSEL when cs_n = '0' and mab = "011" else
                                PxIES when cs_n = '0' and mab = "100" else
                                PxIE  when cs_n = '0' and mab = "101" else
                                PxIFG when cs_n = '0' and mab = "110" else
                                (others => '0');
 
-------------------------------------------------------------------------------------
-- EXTERNAL PORTS
-------------------------------------------------------------------------------------
 
        -- PnOEN
        gen_PnOEN: for i in 0 to 7 generate
        begin
                -- PnOEN(i) <= NOT (MODxDIR(i)) when PxSEL(i) = '1' else NOT (PxDIR(i));
                PnOEN(i) <= PxDIR(i);
        end generate;
 
        -- PnOUT
        gen_PnOUT: for i in 0 to 7 generate
        begin
                -- PnOUT (i) <= MODxIN(i) when PxSEL(i) = '1' else PxOUT(i);
                PnOUT(i) <= PxOUT(i);
        end generate;
 
        -- PxIN
        PxIN <= PnIN;
 
        irq_en : process(rst_n, clk_s)
        begin
                IF (rst_n = '0') THEN
                         IRQ_S <= '0';
                ELSE
                        if (clk_s'EVENT AND clk_s = '0') THEN    -- falling SCKL edge
                                if (irqAck = '1') then
                                        IRQ_S <= '0';
                                else
                                        if ((PxIE(0) = '1' and PxIFG(0) = '1') or (PxIE(1) = '1' and PxIFG(1) = '1') or (PxIE(2) = '1' and PxIFG(2) = '1') or (PxIE(3) = '1' and PxIFG(3) = '1') or
                        (PxIE(4) = '1' and PxIFG(4) = '1') or (PxIE(5) = '1' and PxIFG(5) = '1') or (PxIE(6) = '1' and PxIFG(6) = '1') or (PxIE(7) = '1' and PxIFG(7) = '1')) then
 
                                                IRQ_S <= '1';
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        irq <= IRQ_S;
END beh;
 
 
 

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Subversion Repositories tinyvliw8

[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [ioport.vhd] - Blame information for rev 10

Line No.	Rev	Author	Line
1	2	steckol	`-- ************************************************************************`
2			`-- * This is a RTL Model of the MSP430 IO ports without interrupt`
3			`-- * functionality`
4			`-- *`
5			`-- * This io-port fits the behavior of the msp430 io-port. The functionality`
6			`-- * of the in- and output lines(the output value is also written to the`
7			`-- * input) is provided by the sgb25v io-pads`
8			`-- *`
9			`-- * author: g.panic - IHP, date: 2011-02-07`
10			`-- * version: 1.1`
11			`-- *`
12			`-- * Revision:`
13			`-- * changed clock behavior, clock used only in connection with mdbwr_n`
14			`-- *`
15			`-- ************************************************************************`
16
17			`library ieee;`
18			`use ieee.std_logic_1164.all;`
19
20			`ENTITY ioport IS`
21			`PORT (`
22			`cs_n : IN STD_LOGIC; -- chip select signal`
23
24			`clk : IN STD_LOGIC;`
25
26			`-- memory interface`
27			`mdbwr_n : IN STD_LOGIC; -- write enable signal`
28			`mdb_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus`
29			`mdb_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus`
30			`mab : IN STD_LOGIC_VECTOR(2 downto 0); -- address registers`
31
32			`-- interrupt interface`
33			`irq : out std_logic;`
34			`irqAck : in std_logic;`
35
36			`-- port interface`
37			`PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)`
38			`PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)`
39			`PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)`
40
41			`rst_n : IN STD_LOGIC`
42			`);`
43			`END ioport;`
44
45			`ARCHITECTURE beh OF ioport IS`
46
47			`SIGNAL PxIN : STD_LOGIC_VECTOR(7 DOWNTO 0);`
48			`SIGNAL PxOUT : STD_LOGIC_VECTOR(7 DOWNTO 0);`
49			`SIGNAL PxDIR : STD_LOGIC_VECTOR(7 DOWNTO 0);`
50			`SIGNAL PxSEL : STD_LOGIC_VECTOR(7 DOWNTO 0);`
51
52			`SIGNAL PxIES : STD_LOGIC_VECTOR(7 DOWNTO 0);`
53			`SIGNAL PxIE : STD_LOGIC_VECTOR(7 DOWNTO 0);`
54			`SIGNAL PxIFG : STD_LOGIC_VECTOR(7 DOWNTO 0);`
55
56			`SIGNAL IRQ_S : STD_LOGIC;`
57	10	steckol	`SIGNAL CLK_S : STD_LOGIC;`
58	2	steckol
59			`SIGNAL ifg_clk : std_logic_vector(7 downto 0);`
60			`SIGNAL int : std_logic_vector(7 downto 0);`
61
62			`BEGIN`
63
64			`CLK_S <= clk;`
65
66			`-------------------------------------------------------------------------------------`
67			`-- INTERRUPTS`
68			`-------------------------------------------------------------------------------------`
69
70			`int_edge_gen: for i in 0 to 7 generate`
71			`begin`
72			`process (PxIN(i), PxSEL(i), PxIES(i))`
73			`begin`
74			`if PxSEL(i) = '0' then`
75			`if PxIES(i) = '0' then`
76			`int(i) <= PxIN(i);`
77			`else`
78			`int(i) <= not(PxIN(i));`
79			`end if;`
80			`else`
81			`int(i) <= '0';`
82			`end if;`
83			`end process;`
84			`end generate;`
85
86			`-- generate access clocks to PxIFG, CPU acces has priority`
87			`ifg_clk_gen: for i in 0 to 7 generate`
88			`begin`
89			`ifg_clk(i) <= not(mdbwr_n) when (cs_n = '0' and mab = "110") else int(i);`
90			`end generate;`
91
92			`-- write PxIFG`
93			`PxIFG_gen: for i in 0 to 7 generate`
94			`begin`
95			`write_ifg : PROCESS (rst_n, ifg_clk(i))`
96			`BEGIN`
97			`IF rst_n = '0' THEN`
98			`PxIFG(i) <= '0';`
99			`ELSE`
100			`IF (ifg_clk(i)'event and ifg_clk(i) = '1') THEN`
101			`IF cs_n = '0' and mab = "110" THEN`
102			`IF mdbwr_n = '0' THEN`
103			`PxIFG(i) <= PxIFG(i) and not(mdb_i(i));`
104			`END IF;`
105			`ELSE`
106			`PxIFG (i) <= '1';`
107			`END IF;`
108			`END IF;`
109			`END IF;`
110			`END PROCESS;`
111			`end generate;`
112
113			`-------------------------------------------------------------------------------------`
114			`-- REGISTERS`
115			`-------------------------------------------------------------------------------------`
116
117
118			`-------------------------------------------------------------------------------------`
119			`-- write registers`
120			`-------------------------------------------------------------------------------------`
121
122			`-- PxDIR`
123			`write_l_proc : PROCESS(rst_n, mdbwr_n)`
124			`BEGIN`
125			`IF rst_n = '0' THEN`
126			`PxDIR <= (OTHERS => '0');`
127			`PxOUT <= (OTHERS => '0');`
128			`PxSEL <= (OTHERS => '0');`
129			`PxIES <= (OTHERS => '0');`
130			`PxIE <= (OTHERS => '0');`
131			`ELSE`
132			`if (mdbwr_n'event and mdbwr_n = '0') then`
133			`IF cs_n = '0' THEN`
134			`CASE mab IS`
135			`WHEN "000" => PxDIR <= mdb_i;`
136			`WHEN "001" => PxOUT <= mdb_i;`
137			`WHEN "011" => PxSEL <= mdb_i;`
138			`WHEN "100" => PxIES <= mdb_i;`
139			`WHEN "101" => PxIE <= mdb_i;`
140			`WHEN others => null;`
141			`END CASE;`
142			`end if;`
143			`end if;`
144			`END IF;`
145			`END PROCESS;`
146
147			`-------------------------------------------------------------------------------------`
148			`-- read registers`
149			`-------------------------------------------------------------------------------------`
150
151			`mdb_o <= PxDIR when cs_n = '0' and mab = "000" else`
152			`PxOUT when cs_n = '0' and mab = "001" else`
153			`PxIN when cs_n = '0' and mab = "010" else`
154			`PxSEL when cs_n = '0' and mab = "011" else`
155			`PxIES when cs_n = '0' and mab = "100" else`
156			`PxIE when cs_n = '0' and mab = "101" else`
157			`PxIFG when cs_n = '0' and mab = "110" else`
158			`(others => '0');`
159
160			`-------------------------------------------------------------------------------------`
161			`-- EXTERNAL PORTS`
162			`-------------------------------------------------------------------------------------`
163
164			`-- PnOEN`
165			`gen_PnOEN: for i in 0 to 7 generate`
166			`begin`
167			`-- PnOEN(i) <= NOT (MODxDIR(i)) when PxSEL(i) = '1' else NOT (PxDIR(i));`
168			`PnOEN(i) <= PxDIR(i);`
169			`end generate;`
170
171			`-- PnOUT`
172			`gen_PnOUT: for i in 0 to 7 generate`
173			`begin`
174			`-- PnOUT (i) <= MODxIN(i) when PxSEL(i) = '1' else PxOUT(i);`
175			`PnOUT(i) <= PxOUT(i);`
176			`end generate;`
177
178			`-- PxIN`
179			`PxIN <= PnIN;`
180
181			`irq_en : process(rst_n, clk_s)`
182			`begin`
183			`IF (rst_n = '0') THEN`
184			`IRQ_S <= '0';`
185			`ELSE`
186			`if (clk_s'EVENT AND clk_s = '0') THEN -- falling SCKL edge`
187			`if (irqAck = '1') then`
188			`IRQ_S <= '0';`
189			`else`
190			`if ((PxIE(0) = '1' and PxIFG(0) = '1') or (PxIE(1) = '1' and PxIFG(1) = '1') or (PxIE(2) = '1' and PxIFG(2) = '1') or (PxIE(3) = '1' and PxIFG(3) = '1') or`
191			`(PxIE(4) = '1' and PxIFG(4) = '1') or (PxIE(5) = '1' and PxIFG(5) = '1') or (PxIE(6) = '1' and PxIFG(6) = '1') or (PxIE(7) = '1' and PxIFG(7) = '1')) then`
192
193			`IRQ_S <= '1';`
194			`end if;`
195			`end if;`
196			`end if;`
197			`end if;`
198			`end process;`
199
200			`irq <= IRQ_S;`
201			`END beh;`
202
203
204