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-------------------------------------------------------------------------------
--
-- Design:  tinyVLIW8 soft-core processor
-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date:    24.10.2013 
-- File:    regSet.vhd
--
-------------------------------------------------------------------------------
--
-- Description : This unit is the register set unit of the 8-bit tinyVLIW8
--               vliw processor. 
--
-------------------------------------------------------------------------------
--
--    Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
-- or - as soon they will be approved by the European Commission - subsequent
-- versions of the EUPL (the "License").
-- You may redistribute this code and/or modify it under the terms of this
-- License.
-- You may not use this work except in compliance with the License.
-- You may obtain a copy of the License at:
--
-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc_regSet is
        port (
                state  : in std_logic_vector(3 downto 0);
 
                reg0   : out std_logic_vector(7 downto 0);
                reg1   : out std_logic_vector(7 downto 0);
                reg2   : out std_logic_vector(7 downto 0);
                reg3   : out std_logic_vector(7 downto 0);
                reg4   : out std_logic_vector(7 downto 0);
                reg5   : out std_logic_vector(7 downto 0);
                reg6   : out std_logic_vector(7 downto 0);
                reg7   : out std_logic_vector(7 downto 0);
 
                irqEn  : in std_logic;
 
                aluDataIn  : in std_logic_vector(7 downto 0);
                aluRegSel  : in std_logic_vector(2 downto 0);
                aluRegEn_n : in std_logic;
 
                ldstDataIn  : in std_logic_vector(7 downto 0);
                ldstRegSel  : in std_logic_vector(2 downto 0);
                ldstRegEn_n : in std_logic;
 
                rst_n  : in std_logic
        );
end vliwProc_regSet;
 
architecture behavior of vliwProc_regSet is
 
        signal irqReg0_s : std_logic_vector(7 downto 0);
        signal irqReg1_s : std_logic_vector(7 downto 0);
        signal irqReg2_s : std_logic_vector(7 downto 0);
        signal irqReg3_s : std_logic_vector(7 downto 0);
        signal irqReg4_s : std_logic_vector(7 downto 0);
        signal irqReg5_s : std_logic_vector(7 downto 0);
 
        signal reg0_s : std_logic_vector(7 downto 0);
        signal reg1_s : std_logic_vector(7 downto 0);
        signal reg2_s : std_logic_vector(7 downto 0);
        signal reg3_s : std_logic_vector(7 downto 0);
        signal reg4_s : std_logic_vector(7 downto 0);
        signal reg5_s : std_logic_vector(7 downto 0);
        signal reg6_s : std_logic_vector(7 downto 0);
        signal reg7_s : std_logic_vector(7 downto 0);
 
        signal aluRegData_s  : std_logic_vector(7 downto 0);
        signal aluRegSel_s   : std_logic_vector(2 downto 0);
        signal aluCommit_s   : std_logic;
        signal ldstRegData_s : std_logic_vector(7 downto 0);
        signal ldstRegSel_s  : std_logic_vector(2 downto 0);
        signal ldstCommit_s  : std_logic;
 
        signal irqEn_s : std_logic;
 
BEGIN
 
        alu_commit_p : process(rst_n, state(2))
        begin
                if (rst_n = '0') then
                        aluRegData_s <= (others => '0');
                        aluRegSel_s <= (others => '0');
 
                        aluCommit_s <= '0';
                else
                        if (state(3)'event and state(3) = '1') then
                                if (aluRegEn_n <= '0') then
                                        aluRegSel_s <= aluRegSel;
                                        aluRegData_s <= aluDataIn;
 
                                        aluCommit_s <= '1';
                                else
                                        aluCommit_s <= '0';
                                end if;
                        end if;
                end if;
        end process;
 
        ldst_commit_p : process(rst_n, state(3))
        begin
                if (rst_n = '0') then
                        ldstRegData_s <= (others => '0');
                        ldstRegSel_s <= (others => '0');
 
                        ldstCommit_s <= '0';
                else
                        if (state(3)'event and state(3) = '1') then
                                if (ldstRegEn_n = '0') then
                                        ldstRegSel_s <= ldstRegSel;
                                        ldstRegData_s <= ldstDataIn;
 
                                        ldstCommit_s <= '1';
                                else
                                        ldstCommit_s <= '0';
                                end if;
                        end if;
                end if;
        end process;
 
        commit_p: process(rst_n, state(3))
        begin
                if (rst_n = '0') then
                        irqReg0_s <= (others => '0');
                        irqReg1_s <= (others => '0');
                        irqReg2_s <= (others => '0');
                        irqReg3_s <= (others => '0');
                        irqReg4_s <= (others => '0');
                        irqReg5_s <= (others => '0');
 
                        reg0_s <= (others => '0');
                        reg1_s <= (others => '0');
                        reg2_s <= (others => '0');
                        reg3_s <= (others => '0');
                        reg4_s <= (others => '0');
                        reg5_s <= (others => '0');
                        reg6_s <= (others => '0');
                        reg7_s <= (others => '0');
                elsif (state(3)'event and state(3) = '0') then
                        if (aluCommit_s = '1') then
                                if (aluRegSel_s = "000") then
                                        if (irqEn_s = '1') then
                                                irqReg0_s <= aluRegData_s;
                                        else
                                                reg0_s <= aluRegData_s;
                                        end if;
                                elsif (aluRegSel_s = "001") then
                                        if (irqEn_s = '1') then
                                                irqReg1_s <= aluRegData_s;
                                        else
                                                reg1_s <= aluRegData_s;
                                        end if;
                                elsif (aluRegSel_s = "010") then
                                        if (irqEn_s = '1') then
                                                irqReg2_s <= aluRegData_s;
                                        else
                                                reg2_s <= aluRegData_s;
                                        end if;
                                elsif (aluRegSel_s = "011") then
                                        if (irqEn_s = '1') then
                                                irqReg3_s <= aluRegData_s;
                                        else
                                                reg3_s <= aluRegData_s;
                                        end if;
                                elsif (aluRegSel_s = "100") then
                                        if (irqEn_s = '1') then
                                                irqReg4_s <= aluRegData_s;
                                        else
                                                reg4_s <= aluRegData_s;
                                        end if;
                                elsif (aluRegSel_s = "101") then
                                        if (irqEn_s = '1') then
                                                irqReg5_s <= aluRegData_s;
                                        else
                                                reg5_s <= aluRegData_s;
                                        end if;
                                elsif (aluRegSel_s = "110") then
                                        reg6_s <= aluRegData_s;
                                elsif (aluRegSel_s = "111") then
                                        reg7_s <= aluRegData_s;
                                end if;
                        end if;
 
                        if (ldstCommit_s = '1') then
                                if (ldstRegSel_s = "000") then
                                        if (irqEn_s = '1') then
                                                irqReg0_s <= ldstRegData_s;
                                        else
                                                reg0_s <= ldstRegData_s;
                                        end if;
                                elsif (ldstRegSel_s = "001") then
                                        if (irqEn_s = '1') then
                                                irqReg1_s <= ldstRegData_s;
                                        else
                                                reg1_s <= ldstRegData_s;
                                        end if;
                                elsif (ldstRegSel_s = "010") then
                                        if (irqEn_s = '1') then
                                                irqReg2_s <= ldstRegData_s;
                                        else
                                                reg2_s <= ldstRegData_s;
                                        end if;
                                elsif (ldstRegSel_s = "011") then
                                        if (irqEn_s = '1') then
                                                irqReg3_s <= ldstRegData_s;
                                        else
                                                reg3_s <= ldstRegData_s;
                                        end if;
                                elsif (ldstRegSel_s = "100") then
                                        if (irqEn_s = '1') then
                                                irqReg4_s <= ldstRegData_s;
                                        else
                                                reg4_s <= ldstRegData_s;
                                        end if;
                                elsif (ldstRegSel_s = "101") then
                                        if (irqEn_s = '1') then
                                                irqReg5_s <= ldstRegData_s;
                                        else
                                                reg5_s <= ldstRegData_s;
                                        end if;
                                elsif (ldstRegSel_s = "110") then
                                        reg6_s <= ldstRegData_s;
                                elsif (ldstRegSel_s = "111") then
                                        reg7_s <= ldstRegData_s;
                                end if;
                        end if;
                end if;
        end process;
 
        -- commit interrupt signal after commit of registers, but before access of
        -- functional units
        irqEn_proc: process(rst_n, state(1))
        begin
                if (rst_n = '0') then
                        irqEn_s <= '0';
                else
                        if (state(1)'event and state(1) = '0') then
                                irqEn_s <= irqEn;
                        end if;
                end if;
        end process;
 
        -- output including alu fast forward
        reg0 <= irqReg0_s    when irqEn_s = '1' else
                reg0_s;
        reg1 <= irqReg1_s when irqEn_s = '1' else
                reg1_s;
        reg2 <= irqReg2_s when irqEn_s = '1' else
                reg2_s;
        reg3 <= irqReg3_s when irqEn_s = '1' else
                reg3_s;
        reg4 <= irqReg4_s when irqEn_s = '1' else
                reg4_s;
        reg5 <= irqReg5_s when irqEn_s = '1' else
                reg5_s;
        reg6 <= reg6_s;
        reg7 <= reg7_s;
 
END behavior;

Line No.	Rev	Author	Line
1	9	steckol	`-------------------------------------------------------------------------------`
2			`--`
3			`-- Design: tinyVLIW8 soft-core processor`
4			`-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>`
5			`-- Date: 24.10.2013`
6			`-- File: regSet.vhd`
7			`--`
8			`-------------------------------------------------------------------------------`
9			`--`
10			`-- Description : This unit is the register set unit of the 8-bit tinyVLIW8`
11			`-- vliw processor.`
12			`--`
13			`-------------------------------------------------------------------------------`
14			`--`
15			`-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany`
16			`--`
17			`-- This code is free software. It is licensed under the EUPL, Version 1.1`
18			`-- or - as soon they will be approved by the European Commission - subsequent`
19			`-- versions of the EUPL (the "License").`
20			`-- You may redistribute this code and/or modify it under the terms of this`
21			`-- License.`
22			`-- You may not use this work except in compliance with the License.`
23			`-- You may obtain a copy of the License at:`
24			`--`
25			`-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl`
26			`--`
27			`-- Unless required by applicable law or agreed to in writing, software`
28			`-- distributed under the License is distributed on an "AS IS" basis,`
29			`-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.`
30			`-- See the License for the specific language governing permissions and`
31			`-- limitations under the License.`
32			`--`
33			`-------------------------------------------------------------------------------`
34
35	2	steckol	`library ieee;`
36			`use ieee.std_logic_1164.all;`
37			`use ieee.std_logic_arith.all;`
38
39			`entity vliwProc_regSet is`
40			`port (`
41			`state : in std_logic_vector(3 downto 0);`
42
43			`reg0 : out std_logic_vector(7 downto 0);`
44			`reg1 : out std_logic_vector(7 downto 0);`
45			`reg2 : out std_logic_vector(7 downto 0);`
46			`reg3 : out std_logic_vector(7 downto 0);`
47			`reg4 : out std_logic_vector(7 downto 0);`
48			`reg5 : out std_logic_vector(7 downto 0);`
49			`reg6 : out std_logic_vector(7 downto 0);`
50			`reg7 : out std_logic_vector(7 downto 0);`
51
52			`irqEn : in std_logic;`
53
54			`aluDataIn : in std_logic_vector(7 downto 0);`
55			`aluRegSel : in std_logic_vector(2 downto 0);`
56			`aluRegEn_n : in std_logic;`
57
58			`ldstDataIn : in std_logic_vector(7 downto 0);`
59			`ldstRegSel : in std_logic_vector(2 downto 0);`
60			`ldstRegEn_n : in std_logic;`
61
62			`rst_n : in std_logic`
63			`);`
64			`end vliwProc_regSet;`
65
66			`architecture behavior of vliwProc_regSet is`
67
68			`signal irqReg0_s : std_logic_vector(7 downto 0);`
69			`signal irqReg1_s : std_logic_vector(7 downto 0);`
70			`signal irqReg2_s : std_logic_vector(7 downto 0);`
71			`signal irqReg3_s : std_logic_vector(7 downto 0);`
72	9	steckol	`signal irqReg4_s : std_logic_vector(7 downto 0);`
73			`signal irqReg5_s : std_logic_vector(7 downto 0);`
74	2	steckol
75			`signal reg0_s : std_logic_vector(7 downto 0);`
76			`signal reg1_s : std_logic_vector(7 downto 0);`
77			`signal reg2_s : std_logic_vector(7 downto 0);`
78			`signal reg3_s : std_logic_vector(7 downto 0);`
79			`signal reg4_s : std_logic_vector(7 downto 0);`
80			`signal reg5_s : std_logic_vector(7 downto 0);`
81			`signal reg6_s : std_logic_vector(7 downto 0);`
82			`signal reg7_s : std_logic_vector(7 downto 0);`
83
84			`signal aluRegData_s : std_logic_vector(7 downto 0);`
85			`signal aluRegSel_s : std_logic_vector(2 downto 0);`
86			`signal aluCommit_s : std_logic;`
87			`signal ldstRegData_s : std_logic_vector(7 downto 0);`
88			`signal ldstRegSel_s : std_logic_vector(2 downto 0);`
89			`signal ldstCommit_s : std_logic;`
90
91			`signal irqEn_s : std_logic;`
92
93			`BEGIN`
94
95			`alu_commit_p : process(rst_n, state(2))`
96			`begin`
97			`if (rst_n = '0') then`
98			`aluRegData_s <= (others => '0');`
99			`aluRegSel_s <= (others => '0');`
100
101			`aluCommit_s <= '0';`
102			`else`
103			`if (state(3)'event and state(3) = '1') then`
104			`if (aluRegEn_n <= '0') then`
105			`aluRegSel_s <= aluRegSel;`
106			`aluRegData_s <= aluDataIn;`
107
108			`aluCommit_s <= '1';`
109			`else`
110			`aluCommit_s <= '0';`
111			`end if;`
112			`end if;`
113			`end if;`
114			`end process;`
115
116			`ldst_commit_p : process(rst_n, state(3))`
117			`begin`
118			`if (rst_n = '0') then`
119			`ldstRegData_s <= (others => '0');`
120			`ldstRegSel_s <= (others => '0');`
121
122			`ldstCommit_s <= '0';`
123			`else`
124			`if (state(3)'event and state(3) = '1') then`
125			`if (ldstRegEn_n = '0') then`
126			`ldstRegSel_s <= ldstRegSel;`
127			`ldstRegData_s <= ldstDataIn;`
128
129			`ldstCommit_s <= '1';`
130			`else`
131			`ldstCommit_s <= '0';`
132			`end if;`
133			`end if;`
134			`end if;`
135			`end process;`
136
137			`commit_p: process(rst_n, state(3))`
138			`begin`
139			`if (rst_n = '0') then`
140			`irqReg0_s <= (others => '0');`
141			`irqReg1_s <= (others => '0');`
142			`irqReg2_s <= (others => '0');`
143			`irqReg3_s <= (others => '0');`
144	9	steckol	`irqReg4_s <= (others => '0');`
145			`irqReg5_s <= (others => '0');`
146	2	steckol
147			`reg0_s <= (others => '0');`
148			`reg1_s <= (others => '0');`
149			`reg2_s <= (others => '0');`
150			`reg3_s <= (others => '0');`
151			`reg4_s <= (others => '0');`
152			`reg5_s <= (others => '0');`
153			`reg6_s <= (others => '0');`
154			`reg7_s <= (others => '0');`
155			`elsif (state(3)'event and state(3) = '0') then`
156			`if (aluCommit_s = '1') then`
157			`if (aluRegSel_s = "000") then`
158			`if (irqEn_s = '1') then`
159			`irqReg0_s <= aluRegData_s;`
160			`else`
161			`reg0_s <= aluRegData_s;`
162			`end if;`
163			`elsif (aluRegSel_s = "001") then`
164			`if (irqEn_s = '1') then`
165			`irqReg1_s <= aluRegData_s;`
166			`else`
167			`reg1_s <= aluRegData_s;`
168			`end if;`
169			`elsif (aluRegSel_s = "010") then`
170			`if (irqEn_s = '1') then`
171			`irqReg2_s <= aluRegData_s;`
172			`else`
173			`reg2_s <= aluRegData_s;`
174			`end if;`
175			`elsif (aluRegSel_s = "011") then`
176			`if (irqEn_s = '1') then`
177			`irqReg3_s <= aluRegData_s;`
178			`else`
179			`reg3_s <= aluRegData_s;`
180			`end if;`
181			`elsif (aluRegSel_s = "100") then`
182	9	steckol	`if (irqEn_s = '1') then`
183			`irqReg4_s <= aluRegData_s;`
184			`else`
185			`reg4_s <= aluRegData_s;`
186			`end if;`
187	2	steckol	`elsif (aluRegSel_s = "101") then`
188	9	steckol	`if (irqEn_s = '1') then`
189			`irqReg5_s <= aluRegData_s;`
190			`else`
191			`reg5_s <= aluRegData_s;`
192			`end if;`
193	2	steckol	`elsif (aluRegSel_s = "110") then`
194			`reg6_s <= aluRegData_s;`
195			`elsif (aluRegSel_s = "111") then`
196			`reg7_s <= aluRegData_s;`
197			`end if;`
198			`end if;`
199
200			`if (ldstCommit_s = '1') then`
201			`if (ldstRegSel_s = "000") then`
202			`if (irqEn_s = '1') then`
203			`irqReg0_s <= ldstRegData_s;`
204			`else`
205			`reg0_s <= ldstRegData_s;`
206			`end if;`
207			`elsif (ldstRegSel_s = "001") then`
208			`if (irqEn_s = '1') then`
209			`irqReg1_s <= ldstRegData_s;`
210			`else`
211			`reg1_s <= ldstRegData_s;`
212			`end if;`
213			`elsif (ldstRegSel_s = "010") then`
214			`if (irqEn_s = '1') then`
215			`irqReg2_s <= ldstRegData_s;`
216			`else`
217			`reg2_s <= ldstRegData_s;`
218			`end if;`
219			`elsif (ldstRegSel_s = "011") then`
220			`if (irqEn_s = '1') then`
221			`irqReg3_s <= ldstRegData_s;`
222			`else`
223			`reg3_s <= ldstRegData_s;`
224			`end if;`
225			`elsif (ldstRegSel_s = "100") then`
226	9	steckol	`if (irqEn_s = '1') then`
227			`irqReg4_s <= ldstRegData_s;`
228			`else`
229			`reg4_s <= ldstRegData_s;`
230			`end if;`
231	2	steckol	`elsif (ldstRegSel_s = "101") then`
232	9	steckol	`if (irqEn_s = '1') then`
233			`irqReg5_s <= ldstRegData_s;`
234			`else`
235			`reg5_s <= ldstRegData_s;`
236			`end if;`
237	2	steckol	`elsif (ldstRegSel_s = "110") then`
238			`reg6_s <= ldstRegData_s;`
239			`elsif (ldstRegSel_s = "111") then`
240			`reg7_s <= ldstRegData_s;`
241			`end if;`
242			`end if;`
243			`end if;`
244			`end process;`
245
246			`-- commit interrupt signal after commit of registers, but before access of`
247			`-- functional units`
248			`irqEn_proc: process(rst_n, state(1))`
249			`begin`
250			`if (rst_n = '0') then`
251			`irqEn_s <= '0';`
252			`else`
253			`if (state(1)'event and state(1) = '0') then`
254			`irqEn_s <= irqEn;`
255			`end if;`
256			`end if;`
257			`end process;`
258
259			`-- output including alu fast forward`
260			`reg0 <= irqReg0_s when irqEn_s = '1' else`
261			`reg0_s;`
262			`reg1 <= irqReg1_s when irqEn_s = '1' else`
263			`reg1_s;`
264			`reg2 <= irqReg2_s when irqEn_s = '1' else`
265			`reg2_s;`
266			`reg3 <= irqReg3_s when irqEn_s = '1' else`
267			`reg3_s;`
268	9	steckol	`reg4 <= irqReg4_s when irqEn_s = '1' else`
269			`reg4_s;`
270			`reg5 <= irqReg5_s when irqEn_s = '1' else`
271			`reg5_s;`
272	2	steckol	`reg6 <= reg6_s;`
273			`reg7 <= reg7_s;`
274
275			`END behavior;`

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[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [proc/] [regSet.vhd] - Blame information for rev 9