Subversion Repositories tinyvliw8

-------------------------------------------------------------------------------

--

-- Design:  tinyVLIW8 soft-core processor

-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com>

-- Date:    24.10.2013 

-- File:    vliwProc.vhd

--

-------------------------------------------------------------------------------

--

-- Description : This unit is the VLIW processor core.

--

-------------------------------------------------------------------------------

--

--    Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany

--

-- This code is free software. It is licensed under the EUPL, Version 1.1

-- or - as soon they will be approved by the European Commission - subsequent

-- versions of the EUPL (the "License").

-- You may redistribute this code and/or modify it under the terms of this

-- License.

-- You may not use this work except in compliance with the License.

-- You may obtain a copy of the License at:

--

-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl

--

-- Unless required by applicable law or agreed to in writing, software

-- distributed under the License is distributed on an "AS IS" basis,

-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-- See the License for the specific language governing permissions and

-- limitations under the License.

--

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity vliwProc is

        port (

                -- clock input

                clk           : in std_logic;

                -- instruction bus

                instMemAddr   : out std_logic_vector(10 downto 0);

                instMemDataIn : in  std_logic_vector(31 downto 0);

                instMemEn_n   : out std_logic;

                -- IO bus

                ioMemAddr    : out std_logic_vector(7 downto 0);

                ioMemDataOut : out std_logic_vector(7 downto 0);

                ioMemDataIn  : in  std_logic_vector(7 downto 0);

                ioMemWr_n    : out std_logic;

                ioMemEn_n    : out std_logic;

                -- IO bus

                dataMemAddr    : out std_logic_vector(7 downto 0);

                dataMemDataOut : out std_logic_vector(7 downto 0);

                dataMemDataIn  : in  std_logic_vector(7 downto 0);

                dataMemWr_n    : out std_logic;

                dataMemEn_n    : out std_logic;

                -- interrupt handling

                irqLine        : in  std_logic_vector(4 downto 0);

                irqLineAck     : out std_logic_vector(4 downto 0);

                -- irqEn          : out std_logic;

                -- process stall signals and stall acknowledgment

                stall_n      : in std_logic;

                stalled_n    : out std_logic;

                -- reset input

                rst_n        : in std_logic

        );

end vliwProc;

architecture behavior of vliwProc is

component vliwProc_instDecoder

        port (

                clk       : in std_logic;

                instData  : in  std_logic_vector(31 downto 0);

                ldstOpCode : out std_logic;

                ldstAs     : out std_logic_vector(1 downto 0);

                ldstDstReg : out std_logic_vector(2 downto 0);

                ldstSrc    : out std_logic_vector(7 downto 0);

                ldstEn_n   : out std_logic;

                aluOpCode  : out std_logic_vector(2 downto 0);

                aluAs      : out std_logic_vector(1 downto 0);

                aluDstReg  : out std_logic_vector(2 downto 0);

                aluSrc     : out std_logic_vector(7 downto 0);

                aluEn_n    : out std_logic;

                jmpAs      : out std_logic_vector(1 downto 0);

                jmpDstReg  : out std_logic_vector(10 downto 0);

                jmpEn_n    : out std_logic;

                esb       : out std_logic_vector(3 downto 0);

                stall_n   : in std_logic;

                stalled_n : out std_logic;

                rst_n     : in std_logic

        );

end component;

component vliwProc_statusReg

        port (

                state      : in std_logic_vector(3 downto 0);

                iretEn_n   : in std_logic;

                ioEn_n     : in std_logic;

                irqEn      : in std_logic;

                flagsEn_n  : in std_logic;

                flagsIn    : in std_logic_vector(1 downto 0);       -- carry | zero

                dataIn     : in  std_logic_vector(7 downto 0);

                dataOut    : out std_logic_vector(7 downto 0);

                rst_n      : in std_logic

        );

end component;

component vliwProc_pcReg

        port (

           addrOut    : out std_logic_vector(10 downto 0);

                state      : in std_logic_vector(3 downto 0);

                stalled_n  : in std_logic;

                ioAddr     : in std_logic_vector(1 downto 0);

                ioIn       : in std_logic_vector(7 downto 0);

                ioOut      : out std_logic_vector(7 downto 0);

                ioInEn_n   : in std_logic;

                ioInWr_n   : in std_logic;

                pcLoad_n   : out std_logic;

                jmpIn      : in std_logic_vector(10 downto 0);

                jmpInEn_n  : in std_logic;

                irq        : in std_logic;

                irqAddr    : in std_logic_vector(1 downto 0);

                rst_n      : in std_logic

        );

end component;

component vliwProc_regSet

        port (

                state  : in std_logic_vector(3 downto 0);

                reg0   : out std_logic_vector(7 downto 0);

                reg1   : out std_logic_vector(7 downto 0);

                reg2   : out std_logic_vector(7 downto 0);

                reg3   : out std_logic_vector(7 downto 0);

                reg4   : out std_logic_vector(7 downto 0);

                reg5   : out std_logic_vector(7 downto 0);

                reg6   : out std_logic_vector(7 downto 0);

                reg7   : out std_logic_vector(7 downto 0);

                irqEn  : in std_logic;

                aluDataIn  : in std_logic_vector(7 downto 0);

                aluRegSel  : in std_logic_vector(2 downto 0);

                aluRegEn_n : in std_logic;

                ldstDataIn  : in std_logic_vector(7 downto 0);

                ldstRegSel  : in std_logic_vector(2 downto 0);

                ldstRegEn_n : in std_logic;

                rst_n  : in std_logic

        );

end component;

component vliwProc_loadStore

        port (

                addr     : out std_logic_vector(7 downto 0);

                dataOut  : out std_logic_vector(7 downto 0);

                ioWr_n   : out std_logic;

                ioEn_n   : out std_logic;

                dataWr_n : out std_logic;

                dataEn_n : out std_logic;

                dataIn   : in std_logic_vector(7 downto 0);

                ioIn     : in std_logic_vector(7 downto 0);

                opCode   : in std_logic;

                as       : in std_logic_vector(1 downto 0);

                dstReg   : in std_logic_vector(2 downto 0);

                src      : in std_logic_vector(7 downto 0);

                cs_n     : in std_logic;

                state    : in std_logic_vector(3 downto 0);

                regOut  : out std_logic_vector(7 downto 0);

                reg0     : in std_logic_vector(7 downto 0);

                reg1     : in std_logic_vector(7 downto 0);

                reg2     : in std_logic_vector(7 downto 0);

                reg3     : in std_logic_vector(7 downto 0);

                reg4     : in std_logic_vector(7 downto 0);

                reg5     : in std_logic_vector(7 downto 0);

                reg6     : in std_logic_vector(7 downto 0);

                reg7     : in std_logic_vector(7 downto 0);

                regSel   : out std_logic_vector(2 downto 0);

                regEn_n  : out std_logic;

                rst_n    : in std_logic

        );

end component;

component vliwProc_jmpExec

        port (

                en_n      : in std_logic;

                esb       : in std_logic_vector(3 downto 0);

                dst       : in std_logic_vector(10 downto 0);

                as        : in std_logic_vector(1 downto 0);

                jmpDst    : out std_logic_vector(10 downto 0);

                jmpEn_n   : out std_logic;

                cz        : in std_logic_vector(1 downto 0);

                rst_n     : in std_logic

        );

end component;

component vliwProc_alu

        port (

                state      : in std_logic_vector(3 downto 0);

                enable_n   : in std_logic;

                opcode     : in std_logic_vector(2 downto 0);

                as         : in std_logic_vector(1 downto 0);

                dstRegIn   : in std_logic_vector(2 downto 0);

                dataIn     : in std_logic_vector(7 downto 0);

                reg0       : in std_logic_vector(7 downto 0);

                reg1       : in std_logic_vector(7 downto 0);

                reg2       : in std_logic_vector(7 downto 0);

                reg3       : in std_logic_vector(7 downto 0);

                reg4       : in std_logic_vector(7 downto 0);

                reg5       : in std_logic_vector(7 downto 0);

                reg6       : in std_logic_vector(7 downto 0);

                reg7       : in std_logic_vector(7 downto 0);

                cIn        : in  std_logic;

                cOut       : out std_logic;

                zOut       : out std_logic;

                dstRegEn_n : out std_logic;

                dstRegOut  : out std_logic_vector(2 downto 0);

                dataOut    : out std_logic_vector(7 downto 0);

                rst_n      : in  std_logic

        );

end component;

component vliwProc_irqCntl

        port (

                state      : in std_logic_vector(3 downto 0);

                stalled_n  : in std_logic;

                irqLineIn  : in  std_logic_vector(5 downto 0);

                irqLineOut : out std_logic_vector(5 downto 0);

                irqAck     : out std_logic;

                irqAddr    : out std_logic_vector(1 downto 0);

                ioDataIn   : in std_logic_vector(7 downto 0);

                ioDataOut  : out std_logic_vector(7 downto 0);

                ioInEn_n   : in std_logic;

                ioInWr_n   : in std_logic;

                enable     : in std_logic;

                -- reset input

                rst_n      : in std_logic

        );

end component;

        signal rst_n_s       : std_logic;

        signal stall_n_s     : std_logic;

        signal stalled_n_s   : std_logic;

        signal instAddr_s       : std_logic_vector(10 downto 0);

        signal instDataIn_s     : std_logic_vector(31 downto 0);

        signal pcReg_ioOut_s    : std_logic_vector(7 downto 0);

        signal pcReg_ioInEn_n_s : std_logic;

        signal pcReg_ioInWr_n_s : std_logic;

        signal dataAddr_s    : std_logic_vector(7 downto 0);

        signal ioDataIn_s    : std_logic_vector(7 downto 0);

        signal ioWr_n_s      : std_logic;

        signal ioEn_n_s      : std_logic;

        signal dataOut_s     : std_logic_vector(7 downto 0);

        signal dataIn_s      : std_logic_vector(7 downto 0);

        signal dataWr_n_s    : std_logic;

        signal dataEn_n_s    : std_logic;

        signal ldstOpCode_s : std_logic;

        signal ldstAs_s     : std_logic_vector(1 downto 0);

        signal ldstDstReg_s : std_logic_vector(2 downto 0);

        signal ldstSrc_s    : std_logic_vector(7 downto 0);

        signal ldstEn_n_s   : std_logic;

        signal aluOpCode_s  : std_logic_vector(2 downto 0);

        signal aluAs_s      : std_logic_vector(1 downto 0);

        signal aluDstReg_s  : std_logic_vector(2 downto 0);

        signal aluSrc_s     : std_logic_vector(7 downto 0);

        signal aluEn_n_s    : std_logic;

        signal jmpAs_s      : std_logic_vector(1 downto 0);

        signal jmpDstReg_s  : std_logic_vector(10 downto 0);

        signal jmpEn_n_s    : std_logic;

        signal state_s     : std_logic_vector(3 downto 0);

        signal reg0_s        : std_logic_vector(7 downto 0);

        signal reg1_s        : std_logic_vector(7 downto 0);

        signal reg2_s        : std_logic_vector(7 downto 0);

        signal reg3_s        : std_logic_vector(7 downto 0);

        signal reg4_s        : std_logic_vector(7 downto 0);

        signal reg5_s        : std_logic_vector(7 downto 0);

        signal reg6_s        : std_logic_vector(7 downto 0);

        signal reg7_s        : std_logic_vector(7 downto 0);

        signal ldStRegSel_s    : std_logic_vector(2 downto 0);

        signal ldStRegOut_s    : std_logic_vector(7 downto 0);

        signal ldStRegEn_n_s   : std_logic;

        signal ldstIoEnOut_n_s : std_logic;

        signal ldstIoWrOut_n_s : std_logic;

        signal ldstRst_n_s     : std_logic;

        signal aluRegEn_n_s  : std_logic;

        signal aluFlags_s    : std_logic_vector(1 downto 0);

        signal aluRegSel_s   : std_logic_vector(2 downto 0);

        signal aluRegOut_s   : std_logic_vector(7 downto 0);

        signal pcLoad_n_s    : std_logic;

        signal jmpOutEn_n_s  : std_logic;

        signal jmpAddr_s     : std_logic_vector(10 downto 0);

        signal irqAck_s       : std_logic;

        signal irqAddr_s      : std_logic_vector(1 downto 0);

        signal irqLine_s      : std_logic_vector(5 downto 0);

        signal irqLineAck_s   : std_logic_vector(5 downto 0);

        signal irq_ioOut_s    : std_logic_vector(7 downto 0);

        signal irq_ioInEn_n_s : std_logic;

        signal irq_ioInWr_n_s : std_logic;

        signal statusRegData_s   : std_logic_vector(7 downto 0);

        signal statusRegIoEn_n_s : std_logic;

        signal instMemEn_n_s : std_logic;

        signal instMemClk_s  : std_logic;

begin

        rst_n_s <= rst_n;

        stall_n_s <= stall_n and not(statusRegData_s(7));

        stalled_n <= stalled_n_s;

        instMemAddr   <= instAddr_s;

        instMemEn_n   <= instMemEn_n_s;

        instDataIn_s  <= instMemDataIn;

        -- irqEn <= statusRegData_s(0);

        instMemEn_n_s <= '1' when rst_n = '0' or state_s(3) = '1' or (stall_n_s = '0') else

                         '0';

        ------------------------------------------------------------------------------------------

        --

        -- register Set

        --

        ------------------------------------------------------------------------------------------

        vliwProc_regSet_i : vliwProc_regSet

        port map (

                state  => state_s,

                reg0   => reg0_s,

                reg1   => reg1_s,

                reg2   => reg2_s,

                reg3   => reg3_s,

                reg4   => reg4_s,

                reg5   => reg5_s,

                reg6   => reg6_s,

                reg7   => reg7_s,

                aluDataIn  => aluRegOut_s,

                aluRegSel  => aluRegSel_s,

                aluRegEn_n => aluRegEn_n_s,

                ldstDataIn  => ldStRegOut_s,

                ldstRegSel  => ldStRegSel_s,

                ldstRegEn_n => ldstRegEn_n_s,

                irqEn  => statusRegData_s(0),

                rst_n  => rst_n_s

        );

        statusRegIoEn_n_s <= '0' when state_s(3) = '1' and ioWr_n_s = '0' and ioEn_n_s = '0' and dataAddr_s(7 downto 0) = "00000000" else

                             '1';

        vliwProc_statusReg_i : vliwProc_statusReg

        port map (

                state    => state_s,

                iretEn_n  => pcLoad_n_s,

                ioEn_n    => statusRegIoEn_n_s,

                irqEn     => irqAck_s,

                flagsEn_n => aluRegEn_n_s,

                flagsIn  => aluFlags_s,

                dataIn   => dataOut_s,

                dataOut  => statusRegData_s,

                rst_n    => rst_n_s

        );

        pcReg_ioInEn_n_s <= '0' when ioEn_n_s = '0' and dataAddr_s(7 downto 2) = "000100" else

                            '1';

        pcReg_ioInWr_n_s <= '0' when ioWr_n_s = '0' and pcReg_ioInEn_n_s = '0' else

                            '1';

        vliwProc_pcReg_i : vliwProc_pcReg

        port map (

                addrOut   => instAddr_s,

                state     => state_s,

                stalled_n => stalled_n_s,

                ioAddr    => dataAddr_s(1 downto 0),

                ioIn      => dataOut_s,

                ioOut     => pcReg_ioOut_s,

                ioInEn_n  => pcReg_ioInEn_n_s,

                ioInWr_n  => pcReg_ioInWr_n_s,

                pcLoad_n  => pcLoad_n_s,

                jmpIn     => jmpAddr_s,

                jmpInEn_n => jmpOutEn_n_s,

                irq       => irqAck_s,

                irqAddr   => irqAddr_s,

                rst_n     => rst_n_s

        );

        vliwProc_jmpExec_i : vliwProc_jmpExec

        port map (

                en_n      => jmpEn_n_s,

                esb       => state_s,

                dst       => jmpDstReg_s,

                as        => jmpAs_s,

                jmpDst    => jmpAddr_s,

                jmpEn_n   => jmpOutEn_n_s,

                cz        => statusRegData_s(5 downto 4),

                rst_n     => rst_n_s

        );

        vliwProc_instDecoder_i : vliwProc_instDecoder

        port map (

                clk        => clk,

                esb        => state_s,

                instData   => instDataIn_s,

                ldstOpCode => ldstOpCode_s,

                ldstAs     => ldstAs_s,

                ldstDstReg => ldstDstReg_s,

                ldstSrc    => ldstSrc_s,

                ldstEn_n   => ldstEn_n_s,

                aluOpCode  => aluOpCode_s,

                aluAs      => aluAs_s,

                aluDstReg  => aluDstReg_s,

                aluSrc     => aluSrc_s,

                aluEn_n    => aluEn_n_s,

                jmpAs      => jmpAs_s,

                jmpDstReg  => jmpDstReg_s,

                jmpEn_n    => jmpEn_n_s,

                stall_n    => stall_n_s,

                stalled_n  => stalled_n_s,

                rst_n      => rst_n_s

        );

        ioMemAddr    <= dataAddr_s;

        ioMemDataOut <= dataOut_s;

        ioDataIn_s   <= statusRegData_s when dataAddr_s(7 downto 0) = "00000000" else

                        irq_ioOut_s     when irq_ioInEn_n_s = '0' else

                        pcReg_ioOut_s   when pcReg_ioInEn_n_s = '0'  else

                        ioMemDataIn;

        ioMemWr_n    <= ioWr_n_s when state_s(3) = '1' else

                        '1';

        ioMemEn_n    <= ioEn_n_s;

        dataMemAddr    <= dataAddr_s;

        dataMemDataOut <= dataOut_s;

        dataIn_s       <= dataMemDataIn;

        dataMemWr_n    <= dataWr_n_s when state_s(3) = '1' else

                          '1';

        dataMemEn_n    <= dataEn_n_s;

        ioWr_n_s <= ldstIoWrOut_n_s when rst_n_s = '1' and stalled_n_s = '1' else

                    '1';

        ioEn_n_s <= ldstIoEnOut_n_s when rst_n_s = '1' and stalled_n_s = '1' else

                    '1';

        ldstRst_n_s <= rst_n_s and stalled_n_s;

        vliwProc_loadStore_i : vliwProc_loadStore

        port map (

                addr     => dataAddr_s,

                dataIn   => dataIn_s,

                ioIn     => ioDataIn_s,

                dataOut  => dataOut_s,

                ioWr_n   => ldstIoWrOut_n_s,

                ioEn_n   => ldstIoEnOut_n_s,

                dataWr_n => dataWr_n_s,

                dataEn_n => dataEn_n_s,

                opCode   => ldstOpCode_s,

                as       => ldstAs_s,

                dstReg   => ldstDstReg_s,

                src      => ldstSrc_s,

                cs_n     => ldstEn_n_s,

                state    => state_s,

                regOut   => ldStRegOut_s,

                reg0     => reg0_s,

                reg1     => reg1_s,

                reg2     => reg2_s,

                reg3     => reg3_s,

                reg4     => reg4_s,

                reg5     => reg5_s,

                reg6     => reg6_s,

                reg7     => reg7_s,

                regSel   => ldStRegSel_s,

                regEn_n  => ldStRegEn_n_s,

                rst_n    => ldstRst_n_s

        );

        vliwProc_alu_i : vliwProc_alu

        port map (

                state      => state_s,

                enable_n   => aluEn_n_s,

                opcode     => aluOpCode_s,

                as         => aluAs_s,

                dstRegIn   => aluDstReg_s,

                dataIn     => aluSrc_s,

                reg0       => reg0_s,

                reg1       => reg1_s,

                reg2       => reg2_s,

                reg3       => reg3_s,

                reg4       => reg4_s,

                reg5       => reg5_s,

                reg6       => reg6_s,

                reg7       => reg7_s,

                cIn        => statusRegData_s(5),

                cOut       => aluFlags_s(1),

                zOut       => aluFlags_s(0),

                dstRegEn_n => aluRegEn_n_s,

                dstRegOut  => aluRegSel_s,

                dataOut    => aluRegOut_s,

                rst_n      => rst_n_s

        );

        ------------------------------------------------------------------------------------------

        --

        --   Interrupt handler

        --

        ------------------------------------------------------------------------------------------

        irqLine_s <= '0' & irqLine;

        irqLineAck <= irqLineAck_s(4 downto 0);

        irq_ioInEn_n_s <= '0' when ioEn_n_s = '0' and dataAddr_s(7 downto 0) = "00000001" else

                          '1';

        irq_ioInWr_n_s <= '0' when ioWr_n_s = '0' and irq_ioInEn_n_s = '0' else

                          '1';

        vliwProc_irqCntl_i : vliwProc_irqCntl

        port map (

                state      => state_s,

                stalled_n  => stalled_n_s,

                irqLineIn  => irqLine_s,

                irqLineOut => irqLineAck_s,

                irqAck     => irqAck_s,

                irqAddr    => irqAddr_s,

                ioDataIn   => dataOut_s,

                ioDataOut  => irq_ioOut_s,

                ioInEn_n   => irq_ioInEn_n_s,

                ioInWr_n   => irq_ioInWr_n_s,

                enable     => statusRegData_s(3),

                rst_n      => rst_n_s

        );

end behavior;