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Subversion Repositories tinyvliw8

[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [sysArch.vhd] - Blame information for rev 4

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity sysArch is
        port (
                -- clock input
                clk           : in std_logic;
 
                -- instruction bus
                instMemAddr   : out std_logic_vector(10 downto 0);
                instMemDataIn : in  std_logic_vector(31 downto 0);
                instMemEn_n   : out std_logic;
 
                -- data bus
                dataMemAddr    : out std_logic_vector(7 downto 0);
                dataMemDataIn  : in  std_logic_vector(7 downto 0);
                dataMemDataOut : out std_logic_vector(7 downto 0);
                dataMemEn_n    : out std_logic;
                dataMemWr_n    : out std_logic;
 
                ioAddr    : out std_logic_vector(7 downto 0);
                ioDataIn  : in  std_logic_vector(7 downto 0);
                ioDataOut : out std_logic_vector(7 downto 0);
                ioWrEn_n  : out std_logic;
                ioRdEn_n  : out std_logic;
 
                -- interrupt handling
                irqLine        : in  std_logic;
                irqLineAck     : out std_logic;
 
                -- general purpose IO
                gpio_in  : in  std_logic_vector(7 downto 0);
                gpio_out : out  std_logic_vector(7 downto 0);
                gpio_dir : out  std_logic_vector(7 downto 0);
 
                spi_clk  : OUT STD_LOGIC;       -- SPI clock
                spi_cs   : OUT STD_LOGIC;       -- SPI slave select, active level configurable
                spi_mosi : OUT STD_LOGIC;       -- SPI master output, slave input
                spi_miso : IN  STD_LOGIC;       -- SPI master input, slave output
 
                stall_n      : in std_logic;
                stalled_n    : out std_logic;
 
                -- reset input
                rst_n        : in std_logic
        );
end sysArch;
 
architecture behavior of sysArch is
 
component SPImaster IS
  PORT (
   inclk : IN  STD_LOGIC;       -- system clock
        rst_n : IN  STD_LOGIC;  -- synchr. system reset, high active
-- processor interface
        we_n : IN  STD_LOGIC;   -- write enable, high active
        re_n : IN  STD_LOGIC;   -- read  enable, high active
        addr : IN  STD_LOGIC_VECTOR(1 DOWNTO 0); -- address from processor
        din  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);-- data from processor
        dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-- async. data to processor
        intr : OUT STD_LOGIC;   -- interrupt to processor, high active
        intra : IN STD_LOGIC;   -- interrupt to processor, high active
-- SPI interface
        SCK  : OUT STD_LOGIC;   -- SPI clock
        SS   : OUT STD_LOGIC;   -- SPI slave select, active level configurable
        MOSI : OUT STD_LOGIC;   -- SPI master output, slave input
        MISO : IN  STD_LOGIC    -- SPI master input, slave output
  );
END component;
 
component sha1_ex
  PORT(
    resetn   : IN STD_LOGIC; -- reset the module (low active)
    clk      : IN STD_LOGIC; -- clock of the sha1
    cen     : IN STD_LOGIC; -- IO select low active
    wen      : in std_logic; --- write enable low active
    addr     : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- address signal
    d_in     : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data
    intr     : OUT STD_LOGIC; -- signalizes if generation finished
    intra    : IN STD_LOGIC; -- signalizes if generation finished
    d_out    : out STD_LOGIC_VECTOR(7 DOWNTO 0) -- data
  );
end component;
 
component vliwProc
        port (
                clk            : in  std_logic;
 
                instMemAddr    : out std_logic_vector(10 downto 0);
                instMemDataIn  : in  std_logic_vector(31 downto 0);
                instMemEn_n    : out std_logic;
 
                ioMemAddr    : out std_logic_vector(7 downto 0);
                ioMemDataOut : out std_logic_vector(7 downto 0);
                ioMemDataIn  : in  std_logic_vector(7 downto 0);
                ioMemWr_n    : out std_logic;
                ioMemEn_n    : out std_logic;
 
                -- IO bus
                dataMemAddr    : out std_logic_vector(7 downto 0);
                dataMemDataOut : out std_logic_vector(7 downto 0);
                dataMemDataIn  : in  std_logic_vector(7 downto 0);
                dataMemWr_n    : out std_logic;
                dataMemEn_n    : out std_logic;
 
                irqLine        : in  std_logic_vector(4 downto 0);
                irqLineAck     : out std_logic_vector(4 downto 0);
 
                stall_n      : in std_logic;
                stalled_n    : out std_logic;
 
                rst_n        : in std_logic
        );
end component;
 
component ioport
        port (
                cs_n     : IN  STD_LOGIC;                       -- chip select signal
 
                        clk      : IN  STD_LOGIC;
 
                        -- memory interface
                mdbwr_n  : IN  STD_LOGIC;                    -- write enable signal    
                mdb_i           : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus
                mdb_o           : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus    
                mab     : IN  STD_LOGIC_VECTOR(2 downto 0);      -- address registers 
 
                        irq      : out std_logic;
                        irqAck   : in std_logic;
 
                -- port interface
                PnIN    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
                PnOUT           : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
                PnOEN   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
 
                rst_n           : IN STD_LOGIC
                );
end component;
 
component timer
        PORT (
                clk       : in std_logic;
 
                addr      : in std_logic_vector(2 downto 0);        -- register address
 
                writeEn_n : in  STD_LOGIC;                           -- write enable, low active
                readEn_n  : in  STD_LOGIC;                      -- read enable, low active
 
                dataOut   : OUT std_logic_vector(7 downto 0);    -- data bus for writing register
                dataIn    : IN std_logic_vector(7 downto 0);    -- data bus for reading register
 
                irq       : out std_logic;
                irq_ack   : in  std_logic;
 
                rst_n     : IN  STD_LOGIC                        -- asynchr. reset, low active
        );
end component;
 
        signal clk_s   : std_logic;
 
        signal instAddr_s    : std_logic_vector(10 downto 0);
        signal instDataIn_s  : std_logic_vector(31 downto 0);
        signal instEn_n_s    : std_logic;
 
        -- IO bus
        signal ioAddr_s    : std_logic_vector(7 downto 0);
        signal ioDataOut_s : std_logic_vector(7 downto 0);
        signal ioDataIn_s  : std_logic_vector(7 downto 0);
        signal ioEn_n_s    : std_logic;
        signal ioWr_n_s    : std_logic;
 
        -- GPIO signals
        signal ioDataGpio_s : std_logic_vector(7 downto 0);
        signal ioPortEn_n_s : std_logic;
        signal ioPortIrq_s  : std_logic;
 
        --Fir Data bus
        signal dataAddr_s   : std_logic_vector(7 downto 0);
        signal dataOut_s    : std_logic_vector(7 downto 0);
        signal dataIn_s     : std_logic_vector(7 downto 0);
        signal dataWr_n_s   : std_logic;
        signal dataEn_n_s   : std_logic;
 
        signal rst_n_s     : std_logic;
 
        signal stall_n_s   : std_logic;
        signal stalled_n_s : std_logic;
 
        signal irqLine_s        : std_logic_vector(4 downto 0);
        signal irqLineAck_s     : std_logic_vector(4 downto 0);
 
        -- timer signals 
        signal timer_irq_s      : std_logic;
        signal ioTimerEn_n_s    : std_logic;
        signal ioTimerDataOut_s : std_logic_vector(7 downto 0);
 
        -- spi master signals
        signal ioSpiEn_n_s : std_logic;
        signal spiIrq_s    : std_logic;
        signal ioDataSpi_s : std_logic_vector(7 downto 0);
 
   -- sha1 signals      
        signal ioSha1En_n_s : std_logic;
        signal sha1Irq_s    : std_logic;
        signal ioDataSha1_s : std_logic_vector(7 downto 0);
 
        -- external io interface
        signal ioDataExt_s : std_logic_vector(7 downto 0);
        signal ioExtEn_n_s : std_logic;
 
 
begin
 
        clk_s <= clk;
 
        rst_n_s <= rst_n;
 
        stall_n_s <= stall_n;
        stalled_n <= stalled_n_s;
 
        irqLineAck <= irqLineAck_s(0);   -- export IRQ 0
 
        irqLine_s <= ioPortIrq_s & timer_irq_s & sha1Irq_s & spiIrq_s & irqLine;
 
        instMemAddr  <= instAddr_s;
        instDataIn_s <= instMemDataIn;
        instMemEn_n  <= instEn_n_s;
 
        dataMemAddr    <= dataAddr_s;
        dataIn_s       <= dataMemDataIn;
        dataMemDataOut <= dataOut_s;
        dataMemEn_n    <= dataEn_n_s;
        dataMemWr_n    <= dataWr_n_s;
 
        ioDataIn_s <= ioDataGpio_s     when ioPortEn_n_s = '0' else
                      ioTimerDataOut_s when ioTimerEn_n_s = '0' else
                                          ioDataSpi_s      when ioSpiEn_n_s = '0' else
                                          ioDataSha1_s     when ioSha1En_n_s = '0' else
                                          ioDataExt_s;
 
        vliwProc_i : vliwProc
        port map (
                clk            => clk_s,
 
                instMemAddr    => instAddr_s,
                instMemDataIn  => instDataIn_s,
                instMemEn_n    => instEn_n_s,
 
                ioMemAddr      => ioAddr_s,
                ioMemDataOut   => ioDataOut_s,
                ioMemDataIn    => ioDataIn_s,
                ioMemEn_n      => ioEn_n_s,
                ioMemWr_n      => ioWr_n_s,
 
                dataMemAddr    => dataAddr_s,
                dataMemDataOut => dataOut_s,
                dataMemDataIn  => dataIn_s,
                dataMemEn_n    => dataEn_n_s,
                dataMemWr_n    => dataWr_n_s,
 
                irqLine        => irqLine_s,
                irqLineAck     => irqLineAck_s,
 
                stall_n        => stall_n_s,
                stalled_n      => stalled_n_s,
 
                rst_n          => rst_n_s
        );
 
        ioSpiEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 2) = "000101" else
                       '1';
 
        spiMaster_i : SPImaster
        port map (
                inclk => clk_s,
                rst_n  => rst_n_s,
 
                we_n => ioWr_n_s,
                re_n => ioSpiEn_n_s,
                addr => ioAddr_s(1 downto 0),
                din  => ioDataOut_s,
                dout => ioDataSpi_s,
 
                intr => spiIrq_s,
                intra => irqLineAck_s(1),
 
                SCK  => spi_clk,
                SS   => spi_cs,
                MOSI => spi_mosi,
                MISO => spi_miso
        );
 
        ioSha1En_n_s <= ioEn_n_s when ioAddr_s(7 downto 2) = "000111" else
                        '1';
 
        sha1_i : sha1_ex
        port map (
                resetn   => rst_n_s,
                clk      => clk_s,
                cen        => ioSha1En_n_s,
                wen      => ioWr_n_s,
                addr     => ioAddr_s(1 downto 0),
                d_in     => ioDataOut_s,
                intr     => sha1Irq_s,
                intra    => irqLineAck_s(2),
                d_out    => ioDataSha1_s
        );
 
        ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00100" else
                        '1';
 
        ioport_i : ioport
        port map (
                cs_n     => ioPortEn_n_s,
                clk      => clk_s,
 
                mdbwr_n  => ioWr_n_s,
                mdb_i           => ioDataOut_s,
                mdb_o           => ioDataGpio_s,
                mab     => ioAddr_s(2 downto 0),
 
                irq      => ioPortIrq_s,
                irqAck   => irqLineAck_s(4),
 
                -- port interface
                PnIN    => gpio_in,
                PnOUT           => gpio_out,
                PnOEN   => gpio_dir,
 
                rst_n           => rst_n_s
        );
 
        ioTimerEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00101" else
                         '1';
 
        timer_i : timer
        port map (
                clk       => clk_s,
 
                addr      => ioAddr_s(2 downto 0),
 
                writeEn_n => ioWr_n_s,
                readEn_n  => ioTimerEn_n_s,
 
                dataOut   => ioTimerDataOut_s,
                dataIn    => ioDataOut_s,
 
                irq       => timer_irq_s,
                irq_ack   => irqLineAck_s(3),
 
                rst_n     => rst_n_s
        );
 
        -- external io interface
        ioAddr <= ioAddr_s;
        ioDataOut <= ioDataOut_s;
        ioDataExt_s <= ioDataIn;
        ioRdEn_n <= ioEn_n_s;
        ioWrEn_n <= ioWr_n_s;
 
end behavior;

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Subversion Repositories tinyvliw8

[/] [tinyvliw8/] [trunk/] [src/] [vhdl/] [sysArch.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	steckol	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_arith.all;`
4
5			`entity sysArch is`
6			`port (`
7			`-- clock input`
8			`clk : in std_logic;`
9
10			`-- instruction bus`
11			`instMemAddr : out std_logic_vector(10 downto 0);`
12			`instMemDataIn : in std_logic_vector(31 downto 0);`
13			`instMemEn_n : out std_logic;`
14
15			`-- data bus`
16			`dataMemAddr : out std_logic_vector(7 downto 0);`
17			`dataMemDataIn : in std_logic_vector(7 downto 0);`
18			`dataMemDataOut : out std_logic_vector(7 downto 0);`
19			`dataMemEn_n : out std_logic;`
20			`dataMemWr_n : out std_logic;`
21
22			`ioAddr : out std_logic_vector(7 downto 0);`
23			`ioDataIn : in std_logic_vector(7 downto 0);`
24			`ioDataOut : out std_logic_vector(7 downto 0);`
25			`ioWrEn_n : out std_logic;`
26			`ioRdEn_n : out std_logic;`
27
28			`-- interrupt handling`
29			`irqLine : in std_logic;`
30			`irqLineAck : out std_logic;`
31
32			`-- general purpose IO`
33			`gpio_in : in std_logic_vector(7 downto 0);`
34			`gpio_out : out std_logic_vector(7 downto 0);`
35			`gpio_dir : out std_logic_vector(7 downto 0);`
36
37			`spi_clk : OUT STD_LOGIC; -- SPI clock`
38			`spi_cs : OUT STD_LOGIC; -- SPI slave select, active level configurable`
39			`spi_mosi : OUT STD_LOGIC; -- SPI master output, slave input`
40			`spi_miso : IN STD_LOGIC; -- SPI master input, slave output`
41
42			`stall_n : in std_logic;`
43			`stalled_n : out std_logic;`
44
45			`-- reset input`
46			`rst_n : in std_logic`
47			`);`
48			`end sysArch;`
49
50			`architecture behavior of sysArch is`
51
52			`component SPImaster IS`
53			`PORT (`
54			`inclk : IN STD_LOGIC; -- system clock`
55			`rst_n : IN STD_LOGIC; -- synchr. system reset, high active`
56			`-- processor interface`
57			`we_n : IN STD_LOGIC; -- write enable, high active`
58			`re_n : IN STD_LOGIC; -- read enable, high active`
59			`addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- address from processor`
60			`din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);-- data from processor`
61			`dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-- async. data to processor`
62			`intr : OUT STD_LOGIC; -- interrupt to processor, high active`
63			`intra : IN STD_LOGIC; -- interrupt to processor, high active`
64			`-- SPI interface`
65			`SCK : OUT STD_LOGIC; -- SPI clock`
66			`SS : OUT STD_LOGIC; -- SPI slave select, active level configurable`
67			`MOSI : OUT STD_LOGIC; -- SPI master output, slave input`
68			`MISO : IN STD_LOGIC -- SPI master input, slave output`
69			`);`
70			`END component;`
71
72			`component sha1_ex`
73			`PORT(`
74			`resetn : IN STD_LOGIC; -- reset the module (low active)`
75			`clk : IN STD_LOGIC; -- clock of the sha1`
76			`cen : IN STD_LOGIC; -- IO select low active`
77			`wen : in std_logic; --- write enable low active`
78			`addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- address signal`
79			`d_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data`
80			`intr : OUT STD_LOGIC; -- signalizes if generation finished`
81			`intra : IN STD_LOGIC; -- signalizes if generation finished`
82			`d_out : out STD_LOGIC_VECTOR(7 DOWNTO 0) -- data`
83			`);`
84			`end component;`
85
86			`component vliwProc`
87			`port (`
88			`clk : in std_logic;`
89
90			`instMemAddr : out std_logic_vector(10 downto 0);`
91			`instMemDataIn : in std_logic_vector(31 downto 0);`
92			`instMemEn_n : out std_logic;`
93
94			`ioMemAddr : out std_logic_vector(7 downto 0);`
95			`ioMemDataOut : out std_logic_vector(7 downto 0);`
96			`ioMemDataIn : in std_logic_vector(7 downto 0);`
97			`ioMemWr_n : out std_logic;`
98			`ioMemEn_n : out std_logic;`
99
100			`-- IO bus`
101			`dataMemAddr : out std_logic_vector(7 downto 0);`
102			`dataMemDataOut : out std_logic_vector(7 downto 0);`
103			`dataMemDataIn : in std_logic_vector(7 downto 0);`
104			`dataMemWr_n : out std_logic;`
105			`dataMemEn_n : out std_logic;`
106
107			`irqLine : in std_logic_vector(4 downto 0);`
108			`irqLineAck : out std_logic_vector(4 downto 0);`
109
110			`stall_n : in std_logic;`
111			`stalled_n : out std_logic;`
112
113			`rst_n : in std_logic`
114			`);`
115			`end component;`
116
117			`component ioport`
118			`port (`
119			`cs_n : IN STD_LOGIC; -- chip select signal`
120
121			`clk : IN STD_LOGIC;`
122
123			`-- memory interface`
124			`mdbwr_n : IN STD_LOGIC; -- write enable signal`
125			`mdb_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus`
126			`mdb_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus`
127			`mab : IN STD_LOGIC_VECTOR(2 downto 0); -- address registers`
128
129			`irq : out std_logic;`
130			`irqAck : in std_logic;`
131
132			`-- port interface`
133			`PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)`
134			`PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)`
135			`PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)`
136
137			`rst_n : IN STD_LOGIC`
138			`);`
139			`end component;`
140
141			`component timer`
142			`PORT (`
143			`clk : in std_logic;`
144
145			`addr : in std_logic_vector(2 downto 0); -- register address`
146
147			`writeEn_n : in STD_LOGIC; -- write enable, low active`
148			`readEn_n : in STD_LOGIC; -- read enable, low active`
149
150			`dataOut : OUT std_logic_vector(7 downto 0); -- data bus for writing register`
151			`dataIn : IN std_logic_vector(7 downto 0); -- data bus for reading register`
152
153			`irq : out std_logic;`
154			`irq_ack : in std_logic;`
155
156			`rst_n : IN STD_LOGIC -- asynchr. reset, low active`
157			`);`
158			`end component;`
159
160			`signal clk_s : std_logic;`
161
162			`signal instAddr_s : std_logic_vector(10 downto 0);`
163			`signal instDataIn_s : std_logic_vector(31 downto 0);`
164			`signal instEn_n_s : std_logic;`
165
166			`-- IO bus`
167			`signal ioAddr_s : std_logic_vector(7 downto 0);`
168			`signal ioDataOut_s : std_logic_vector(7 downto 0);`
169			`signal ioDataIn_s : std_logic_vector(7 downto 0);`
170			`signal ioEn_n_s : std_logic;`
171			`signal ioWr_n_s : std_logic;`
172
173			`-- GPIO signals`
174			`signal ioDataGpio_s : std_logic_vector(7 downto 0);`
175			`signal ioPortEn_n_s : std_logic;`
176			`signal ioPortIrq_s : std_logic;`
177
178			`--Fir Data bus`
179			`signal dataAddr_s : std_logic_vector(7 downto 0);`
180			`signal dataOut_s : std_logic_vector(7 downto 0);`
181			`signal dataIn_s : std_logic_vector(7 downto 0);`
182			`signal dataWr_n_s : std_logic;`
183			`signal dataEn_n_s : std_logic;`
184
185			`signal rst_n_s : std_logic;`
186
187			`signal stall_n_s : std_logic;`
188			`signal stalled_n_s : std_logic;`
189
190			`signal irqLine_s : std_logic_vector(4 downto 0);`
191			`signal irqLineAck_s : std_logic_vector(4 downto 0);`
192
193			`-- timer signals`
194			`signal timer_irq_s : std_logic;`
195			`signal ioTimerEn_n_s : std_logic;`
196			`signal ioTimerDataOut_s : std_logic_vector(7 downto 0);`
197
198			`-- spi master signals`
199			`signal ioSpiEn_n_s : std_logic;`
200			`signal spiIrq_s : std_logic;`
201			`signal ioDataSpi_s : std_logic_vector(7 downto 0);`
202
203			`-- sha1 signals`
204			`signal ioSha1En_n_s : std_logic;`
205			`signal sha1Irq_s : std_logic;`
206			`signal ioDataSha1_s : std_logic_vector(7 downto 0);`
207
208			`-- external io interface`
209			`signal ioDataExt_s : std_logic_vector(7 downto 0);`
210			`signal ioExtEn_n_s : std_logic;`
211
212
213			`begin`
214
215			`clk_s <= clk;`
216
217			`rst_n_s <= rst_n;`
218
219			`stall_n_s <= stall_n;`
220			`stalled_n <= stalled_n_s;`
221
222			`irqLineAck <= irqLineAck_s(0); -- export IRQ 0`
223
224			`irqLine_s <= ioPortIrq_s & timer_irq_s & sha1Irq_s & spiIrq_s & irqLine;`
225
226			`instMemAddr <= instAddr_s;`
227			`instDataIn_s <= instMemDataIn;`
228			`instMemEn_n <= instEn_n_s;`
229
230			`dataMemAddr <= dataAddr_s;`
231			`dataIn_s <= dataMemDataIn;`
232			`dataMemDataOut <= dataOut_s;`
233			`dataMemEn_n <= dataEn_n_s;`
234			`dataMemWr_n <= dataWr_n_s;`
235
236			`ioDataIn_s <= ioDataGpio_s when ioPortEn_n_s = '0' else`
237			`ioTimerDataOut_s when ioTimerEn_n_s = '0' else`
238			`ioDataSpi_s when ioSpiEn_n_s = '0' else`
239			`ioDataSha1_s when ioSha1En_n_s = '0' else`
240			`ioDataExt_s;`
241
242			`vliwProc_i : vliwProc`
243			`port map (`
244			`clk => clk_s,`
245
246			`instMemAddr => instAddr_s,`
247			`instMemDataIn => instDataIn_s,`
248			`instMemEn_n => instEn_n_s,`
249
250			`ioMemAddr => ioAddr_s,`
251			`ioMemDataOut => ioDataOut_s,`
252			`ioMemDataIn => ioDataIn_s,`
253			`ioMemEn_n => ioEn_n_s,`
254			`ioMemWr_n => ioWr_n_s,`
255
256			`dataMemAddr => dataAddr_s,`
257			`dataMemDataOut => dataOut_s,`
258			`dataMemDataIn => dataIn_s,`
259			`dataMemEn_n => dataEn_n_s,`
260			`dataMemWr_n => dataWr_n_s,`
261
262			`irqLine => irqLine_s,`
263			`irqLineAck => irqLineAck_s,`
264
265			`stall_n => stall_n_s,`
266			`stalled_n => stalled_n_s,`
267
268			`rst_n => rst_n_s`
269			`);`
270
271			`ioSpiEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 2) = "000101" else`
272			`'1';`
273
274			`spiMaster_i : SPImaster`
275			`port map (`
276			`inclk => clk_s,`
277			`rst_n => rst_n_s,`
278
279			`we_n => ioWr_n_s,`
280			`re_n => ioSpiEn_n_s,`
281			`addr => ioAddr_s(1 downto 0),`
282			`din => ioDataOut_s,`
283			`dout => ioDataSpi_s,`
284
285			`intr => spiIrq_s,`
286			`intra => irqLineAck_s(1),`
287
288			`SCK => spi_clk,`
289			`SS => spi_cs,`
290			`MOSI => spi_mosi,`
291			`MISO => spi_miso`
292			`);`
293
294			`ioSha1En_n_s <= ioEn_n_s when ioAddr_s(7 downto 2) = "000111" else`
295			`'1';`
296
297			`sha1_i : sha1_ex`
298			`port map (`
299			`resetn => rst_n_s,`
300			`clk => clk_s,`
301			`cen => ioSha1En_n_s,`
302			`wen => ioWr_n_s,`
303			`addr => ioAddr_s(1 downto 0),`
304			`d_in => ioDataOut_s,`
305			`intr => sha1Irq_s,`
306			`intra => irqLineAck_s(2),`
307			`d_out => ioDataSha1_s`
308			`);`
309
310			`ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00100" else`
311			`'1';`
312
313			`ioport_i : ioport`
314			`port map (`
315			`cs_n => ioPortEn_n_s,`
316			`clk => clk_s,`
317
318			`mdbwr_n => ioWr_n_s,`
319			`mdb_i => ioDataOut_s,`
320			`mdb_o => ioDataGpio_s,`
321			`mab => ioAddr_s(2 downto 0),`
322
323			`irq => ioPortIrq_s,`
324			`irqAck => irqLineAck_s(4),`
325
326			`-- port interface`
327			`PnIN => gpio_in,`
328			`PnOUT => gpio_out,`
329			`PnOEN => gpio_dir,`
330
331			`rst_n => rst_n_s`
332			`);`
333
334			`ioTimerEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00101" else`
335			`'1';`
336
337			`timer_i : timer`
338			`port map (`
339			`clk => clk_s,`
340
341			`addr => ioAddr_s(2 downto 0),`
342
343			`writeEn_n => ioWr_n_s,`
344			`readEn_n => ioTimerEn_n_s,`
345
346			`dataOut => ioTimerDataOut_s,`
347			`dataIn => ioDataOut_s,`
348
349			`irq => timer_irq_s,`
350			`irq_ack => irqLineAck_s(3),`
351
352			`rst_n => rst_n_s`
353			`);`
354
355			`-- external io interface`
356			`ioAddr <= ioAddr_s;`
357			`ioDataOut <= ioDataOut_s;`
358			`ioDataExt_s <= ioDataIn;`
359			`ioRdEn_n <= ioEn_n_s;`
360			`ioWrEn_n <= ioWr_n_s;`
361
362			`end behavior;`