Subversion Repositories tinyvliw8

library STD;

use std.textio.all;

library IEEE;

use IEEE.std_logic_1164.all;

use ieee.std_logic_textio.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity lib_tb_rom32bit is

        generic ( fileName : string );

        port (

                signal addr    : in std_logic_vector(10 downto 0);

                signal dataOut : out std_logic_vector(31 downto 0);

                signal en_n    : in std_logic

        );

end lib_tb_rom32bit;

architecture beh of lib_tb_rom32bit is

        subtype word is std_logic_vector(31 downto 0);

        type memory is array (0 to ((2**11) - 1)) of word;

        signal rom32bit : memory := ((others => (others => '0')));

        function string_to_slv (s: string) return std_logic_vector is

                variable slv: std_logic_vector(((s'length * 4) - 1) downto 0);

                variable v: std_logic_vector(3 downto 0);

                variable k: integer;

        begin

                k := s'length;

                for i in s'range loop

                    case s(i) is

                                when '0' => v := "0000";

                                when '1' => v := "0001";

                                when '2' => v := "0010";

                                when '3' => v := "0011";

                                when '4' => v := "0100";

                                when '5' => v := "0101";

                                when '6' => v := "0110";

                                when '7' => v := "0111";

                                when '8' => v := "1000";

                                when '9' => v := "1001";

                                when 'a' => v := "1010";

                                when 'b' => v := "1011";

                                when 'c' => v := "1100";

                                when 'd' => v := "1101";

                                when 'e' => v := "1110";

                                when 'f' => v := "1111";

                                when others => v:= "XXXX";

                        end case;

                        slv(((4 * k) - 1) downto (4 * (k - 1))) := v;

                        k := k - 1;

                end loop;

                return slv;

        end string_to_slv;

begin

        initRom : process

                variable romAddrIn : integer range 0 to ((2**11) - 1);

                variable startUp : boolean := true;

                file filePtr : text;

                variable lineNum : line;

                variable lineText : string(1 to 16);

                variable hdrText  : string(1 to 3);

                variable loadField : std_logic_vector(7 downto 0);

                variable loadAddr  : std_logic_vector(15 downto 0);

        begin

                if (startUp = true) then

                        file_open(filePtr, fileName, READ_MODE);

                        while (not endfile(filePtr)) loop

                                readline(filePtr, lineNum);

                                read(lineNum, hdrText);

                                loadField := string_to_slv(hdrText(2 to 3));

                                if (loadField = x"04") then

                                        read(lineNum, lineText);

                                        loadAddr := string_to_slv(lineText(1 to 4));

                                        romAddrIn := conv_integer(loadAddr(10 downto 0));

                                        rom32bit(romAddrIn) <= string_to_slv(lineText(7 to 14));

                                end if;

                                wait for 5 ns;

                        end loop;

                        file_close(filePtr);

                        startUp := false;

                else

                        wait;

                end if;

        end process;

        readRom : process(en_n)

                variable romAddrIn : integer range 0 to ((2**11) - 1);

        begin

                if (en_n = '0') then

                        romAddrIn := conv_integer(addr);

                        dataOut <= rom32bit(romAddrIn) after 7 ns;

                else

                        dataOut <= (others => 'X');

                end if;

        end process;

end beh;