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https://opencores.org/ocsvn/tosnet/tosnet/trunk
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sonicwave |
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-- Company: SDU, Robolab, Denmark
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-- Engineer: Simon Falsig
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--
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-- Create Date: 15:49:43 04/01/2008
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-- Design Name:
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-- Module Name: crcpack - Behavioral
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-- Project Name: TosNet Datalink Layer
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-- Target Devices: Xilinx Spartan3
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-- Tool versions: ISE 9.2.04i
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-- Description:
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-- Adapted from "Parallel CRC Realization", by Guiseppe Campobello, Guiseppe
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-- Patanč and Marco Russo, IEEE Transactions on Computers, Vol.52, No.10,
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-- October 2003.
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-- Adjustments have been made to the layout, and the reset has been converted
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-- to a synchronous reset instead of the asynchronous reset from the original
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-- paper.
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--
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-- Dependencies:
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-- crcgen.vhd (Contains implementation)
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--
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-- Revision:
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-- Revision 1.00 - Working!
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package crcpack is
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constant CRC16 : std_logic_vector(16 downto 0) := "11000000000000101";
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constant CRCXA6 : std_logic_vector(8 downto 0) := "101100101";
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constant CRCDIM : integer := 8;
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constant CRC : std_logic_vector(CRCDIM downto 0) := CRCXA6;
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constant DATA_WIDTH : integer range 1 to CRCDIM := 8;
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type matrix is array (CRCDIM - 1 downto 0) of std_logic_vector (CRCDIM - 1 downto 0);
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end crcpack ;
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