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----------------------------------------------------------------------------------
-- Company:             University of Southern Denmark
-- Engineer:            Simon Falsig
-- 
-- Create Date:         11/5/2010 
-- Design Name:         8b/10b encoder
-- Module Name:         enc_8b10b - Behavioral 
-- File Name:           enc_8b10b.vhd
-- Project Name:        TosNet
-- Target Devices:      Spartan3/6
-- Tool versions:       Xilinx ISE 12.2
-- Description:         An 8b/10b encoder. The complete 8b/10b encoding is not
--                                      implemented though (only the control symbols K.28.1 and 
--                                      K.28.5 are available, all others will just encode as K.28.1).
--                                      This is done to simplify and minimize the code, and as the
--                                      other control codes aren't used by the TosNet physical layer
--                                      anyways.
--
-- Revision: 
-- Revision 3.2 -       Initial release
--
-- Copyright 2010
--
-- This module is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This module is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this module.  If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity enc_8b10b is
port (  clk                                     : in    STD_LOGIC;
                ce                                      : in    STD_LOGIC;
                din                                     : in    STD_LOGIC_VECTOR(7 downto 0);
                dout                            : out   STD_LOGIC_VECTOR(9 downto 0);
                kin                                     : in    STD_LOGIC);
end enc_8b10b;
 
architecture Behavioral of enc_8b10b is
 
        signal rd                               : STD_LOGIC := '0';
        signal next_rd                  : STD_LOGIC;
        signal temp_rd_s0               : STD_LOGIC; --Stage 0
        signal temp_rd_k0               : STD_LOGIC; --Stage 1, k=0
        signal dxA                              : STD_LOGIC;
        signal EDCBA                    : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
        signal HGF                              : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
        signal iedcba                   : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
        signal jhgf                             : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
begin
 
        process(jhgf, iedcba, kin, rd, temp_rd_k0, EDCBA, HGF)
        begin
                if(kin = '0') then
                        dout <= jhgf & iedcba;
                        next_rd <= temp_rd_k0;
                else
                        next_rd <= not rd;
                        if(HGF = "101" and EDCBA = "11100") then
                                if(rd = '0') then
                                        dout <= "0101111100";
                                else
                                        dout <= "1010000011";
                                end if;
                        else            --Transmit K.28.1 => QUIET
                                if(rd = '0') then
                                        dout <= "1001111100";
                                else
                                        dout <= "0110000011";
                                end if;
                        end if;
                end if;
        end process;
 
 
        process(clk)
        begin
                if(clk = '1' and clk'event) then
                        if(ce = '1') then
                                EDCBA <= din(4 downto 0);
                                HGF <= din(7 downto 5);
                                rd <= next_rd;
                        end if;
                end if;
        end process;
 
        process(EDCBA, rd)
        begin
                case EDCBA is
                        when "00000" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "111001";
                                else
                                        iedcba <= "000110";
                                end if;
                        when "00001" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "101110";
                                else
                                        iedcba <= "010001";
                                end if;
                        when "00010" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "101101";
                                else
                                        iedcba <= "010010";
                                end if;
                        when "00011" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "100011";
                        when "00100" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "101011";
                                else
                                        iedcba <= "010100";
                                end if;
                        when "00101" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "100101";
                        when "00110" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "100110";
                        when "00111" =>
                                temp_rd_s0 <= rd;
                                if(rd = '0') then
                                        iedcba <= "000111";
                                else
                                        iedcba <= "111000";
                                end if;
                        when "01000" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "100111";
                                else
                                        iedcba <= "011000";
                                end if;
                        when "01001" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "101001";
                        when "01010" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "101010";
                        when "01011" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "001011";
                        when "01100" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "101100";
                        when "01101" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "001101";
                        when "01110" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "001110";
                        when "01111" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "111010";
                                else
                                        iedcba <= "000101";
                                end if;
                        when "10000" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "110110";
                                else
                                        iedcba <= "001001";
                                end if;
                        when "10001" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "110001";
                        when "10010" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "110010";
                        when "10011" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "010011";
                        when "10100" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "110100";
                        when "10101" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "010101";
                        when "10110" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "010110";
                        when "10111" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "010111";
                                else
                                        iedcba <= "101000";
                                end if;
                        when "11000" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "110011";
                                else
                                        iedcba <= "001100";
                                end if;
                        when "11001" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "011001";
                        when "11010" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "011010";
                        when "11011" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "011011";
                                else
                                        iedcba <= "100100";
                                end if;
                        when "11100" =>
                                temp_rd_s0 <= rd;
                                iedcba <= "011100";
                        when "11101" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "011101";
                                else
                                        iedcba <= "100010";
                                end if;
                        when "11110" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "011110";
                                else
                                        iedcba <= "100001";
                                end if;
                        when "11111" =>
                                temp_rd_s0 <= not rd;
                                if(rd = '0') then
                                        iedcba <= "110101";
                                else
                                        iedcba <= "001010";
                                end if;
                        when others =>
                end case;
        end process;
 
        dxA <= '1' when (((EDCBA = 17 or EDCBA = 18 or EDCBA = 20) and temp_rd_s0 = '0') or
                                         ((EDCBA = 11 or EDCBA = 13 or EDCBA = 14) and temp_rd_s0 = '1'))
                                         else '0';
 
        process(HGF, EDCBA, dxA, temp_rd_s0)
        begin
                case HGF is
                        when "000" =>
                                temp_rd_k0 <= not temp_rd_s0;
                                if(temp_rd_s0 = '0') then
                                        jhgf <= "1101";
                                else
                                        jhgf <= "0010";
                                end if;
                        when "001" =>
                                temp_rd_k0 <= temp_rd_s0;
                                jhgf <= "1001";
                        when "010" =>
                                temp_rd_k0 <= temp_rd_s0;
                                jhgf <= "1010";
                        when "011" =>
                                temp_rd_k0 <= not temp_rd_s0;
                                if(temp_rd_s0 = '0') then
                                        jhgf <= "0011";
                                else
                                        jhgf <= "1100";
                                end if;
                        when "100" =>
                                temp_rd_k0 <= not temp_rd_s0;
                                if(temp_rd_s0 = '0') then
                                        jhgf <= "1011";
                                else
                                        jhgf <= "0100";
                                end if;
                        when "101" =>
                                temp_rd_k0 <= temp_rd_s0;
                                jhgf <= "0101";
                        when "110" =>
                                temp_rd_k0 <= temp_rd_s0;
                                jhgf <= "0110";
                        when "111" =>
                                temp_rd_k0 <= not temp_rd_s0;
                                if(dxA = '0') then
                                        if(temp_rd_s0 = '0') then
                                                jhgf <= "0111";
                                        else
                                                jhgf <= "1000";
                                        end if;
                                else
                                        if(temp_rd_s0 = '0') then
                                                jhgf <= "1110";
                                        else
                                                jhgf <= "0001";
                                        end if;
                                end if;
                        when others =>
                end case;
        end process;
 
 
 
 
end Behavioral;
 

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Line No.	Rev	Author	Line
1	5	sonicwave	`----------------------------------------------------------------------------------`
2			`-- Company: University of Southern Denmark`
3			`-- Engineer: Simon Falsig`
4			`--`
5			`-- Create Date: 11/5/2010`
6			`-- Design Name: 8b/10b encoder`
7			`-- Module Name: enc_8b10b - Behavioral`
8			`-- File Name: enc_8b10b.vhd`
9			`-- Project Name: TosNet`
10			`-- Target Devices: Spartan3/6`
11			`-- Tool versions: Xilinx ISE 12.2`
12			`-- Description: An 8b/10b encoder. The complete 8b/10b encoding is not`
13			`-- implemented though (only the control symbols K.28.1 and`
14			`-- K.28.5 are available, all others will just encode as K.28.1).`
15			`-- This is done to simplify and minimize the code, and as the`
16			`-- other control codes aren't used by the TosNet physical layer`
17			`-- anyways.`
18			`--`
19			`-- Revision:`
20			`-- Revision 3.2 - Initial release`
21			`--`
22			`-- Copyright 2010`
23			`--`
24			`-- This module is free software: you can redistribute it and/or modify`
25			`-- it under the terms of the GNU Lesser General Public License as published by`
26			`-- the Free Software Foundation, either version 3 of the License, or`
27			`-- (at your option) any later version.`
28			`--`
29			`-- This module is distributed in the hope that it will be useful,`
30			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
31			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
32			`-- GNU Lesser General Public License for more details.`
33			`--`
34			`-- You should have received a copy of the GNU Lesser General Public License`
35			`-- along with this module. If not, see <http://www.gnu.org/licenses/>.`
36			`----------------------------------------------------------------------------------`
37			`library IEEE;`
38			`use IEEE.STD_LOGIC_1164.ALL;`
39			`use IEEE.STD_LOGIC_ARITH.ALL;`
40			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
41
42			`entity enc_8b10b is`
43			`port ( clk : in STD_LOGIC;`
44			`ce : in STD_LOGIC;`
45			`din : in STD_LOGIC_VECTOR(7 downto 0);`
46			`dout : out STD_LOGIC_VECTOR(9 downto 0);`
47			`kin : in STD_LOGIC);`
48			`end enc_8b10b;`
49
50			`architecture Behavioral of enc_8b10b is`
51
52			`signal rd : STD_LOGIC := '0';`
53			`signal next_rd : STD_LOGIC;`
54			`signal temp_rd_s0 : STD_LOGIC; --Stage 0`
55			`signal temp_rd_k0 : STD_LOGIC; --Stage 1, k=0`
56			`signal dxA : STD_LOGIC;`
57			`signal EDCBA : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');`
58			`signal HGF : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');`
59			`signal iedcba : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');`
60			`signal jhgf : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');`
61			`begin`
62
63			`process(jhgf, iedcba, kin, rd, temp_rd_k0, EDCBA, HGF)`
64			`begin`
65			`if(kin = '0') then`
66			`dout <= jhgf & iedcba;`
67			`next_rd <= temp_rd_k0;`
68			`else`
69			`next_rd <= not rd;`
70			`if(HGF = "101" and EDCBA = "11100") then`
71			`if(rd = '0') then`
72			`dout <= "0101111100";`
73			`else`
74			`dout <= "1010000011";`
75			`end if;`
76			`else --Transmit K.28.1 => QUIET`
77			`if(rd = '0') then`
78			`dout <= "1001111100";`
79			`else`
80			`dout <= "0110000011";`
81			`end if;`
82			`end if;`
83			`end if;`
84			`end process;`
85
86
87			`process(clk)`
88			`begin`
89			`if(clk = '1' and clk'event) then`
90			`if(ce = '1') then`
91			`EDCBA <= din(4 downto 0);`
92			`HGF <= din(7 downto 5);`
93			`rd <= next_rd;`
94			`end if;`
95			`end if;`
96			`end process;`
97
98			`process(EDCBA, rd)`
99			`begin`
100			`case EDCBA is`
101			`when "00000" =>`
102			`temp_rd_s0 <= not rd;`
103			`if(rd = '0') then`
104			`iedcba <= "111001";`
105			`else`
106			`iedcba <= "000110";`
107			`end if;`
108			`when "00001" =>`
109			`temp_rd_s0 <= not rd;`
110			`if(rd = '0') then`
111			`iedcba <= "101110";`
112			`else`
113			`iedcba <= "010001";`
114			`end if;`
115			`when "00010" =>`
116			`temp_rd_s0 <= not rd;`
117			`if(rd = '0') then`
118			`iedcba <= "101101";`
119			`else`
120			`iedcba <= "010010";`
121			`end if;`
122			`when "00011" =>`
123			`temp_rd_s0 <= rd;`
124			`iedcba <= "100011";`
125			`when "00100" =>`
126			`temp_rd_s0 <= not rd;`
127			`if(rd = '0') then`
128			`iedcba <= "101011";`
129			`else`
130			`iedcba <= "010100";`
131			`end if;`
132			`when "00101" =>`
133			`temp_rd_s0 <= rd;`
134			`iedcba <= "100101";`
135			`when "00110" =>`
136			`temp_rd_s0 <= rd;`
137			`iedcba <= "100110";`
138			`when "00111" =>`
139			`temp_rd_s0 <= rd;`
140			`if(rd = '0') then`
141			`iedcba <= "000111";`
142			`else`
143			`iedcba <= "111000";`
144			`end if;`
145			`when "01000" =>`
146			`temp_rd_s0 <= not rd;`
147			`if(rd = '0') then`
148			`iedcba <= "100111";`
149			`else`
150			`iedcba <= "011000";`
151			`end if;`
152			`when "01001" =>`
153			`temp_rd_s0 <= rd;`
154			`iedcba <= "101001";`
155			`when "01010" =>`
156			`temp_rd_s0 <= rd;`
157			`iedcba <= "101010";`
158			`when "01011" =>`
159			`temp_rd_s0 <= rd;`
160			`iedcba <= "001011";`
161			`when "01100" =>`
162			`temp_rd_s0 <= rd;`
163			`iedcba <= "101100";`
164			`when "01101" =>`
165			`temp_rd_s0 <= rd;`
166			`iedcba <= "001101";`
167			`when "01110" =>`
168			`temp_rd_s0 <= rd;`
169			`iedcba <= "001110";`
170			`when "01111" =>`
171			`temp_rd_s0 <= not rd;`
172			`if(rd = '0') then`
173			`iedcba <= "111010";`
174			`else`
175			`iedcba <= "000101";`
176			`end if;`
177			`when "10000" =>`
178			`temp_rd_s0 <= not rd;`
179			`if(rd = '0') then`
180			`iedcba <= "110110";`
181			`else`
182			`iedcba <= "001001";`
183			`end if;`
184			`when "10001" =>`
185			`temp_rd_s0 <= rd;`
186			`iedcba <= "110001";`
187			`when "10010" =>`
188			`temp_rd_s0 <= rd;`
189			`iedcba <= "110010";`
190			`when "10011" =>`
191			`temp_rd_s0 <= rd;`
192			`iedcba <= "010011";`
193			`when "10100" =>`
194			`temp_rd_s0 <= rd;`
195			`iedcba <= "110100";`
196			`when "10101" =>`
197			`temp_rd_s0 <= rd;`
198			`iedcba <= "010101";`
199			`when "10110" =>`
200			`temp_rd_s0 <= rd;`
201			`iedcba <= "010110";`
202			`when "10111" =>`
203			`temp_rd_s0 <= not rd;`
204			`if(rd = '0') then`
205			`iedcba <= "010111";`
206			`else`
207			`iedcba <= "101000";`
208			`end if;`
209			`when "11000" =>`
210			`temp_rd_s0 <= not rd;`
211			`if(rd = '0') then`
212			`iedcba <= "110011";`
213			`else`
214			`iedcba <= "001100";`
215			`end if;`
216			`when "11001" =>`
217			`temp_rd_s0 <= rd;`
218			`iedcba <= "011001";`
219			`when "11010" =>`
220			`temp_rd_s0 <= rd;`
221			`iedcba <= "011010";`
222			`when "11011" =>`
223			`temp_rd_s0 <= not rd;`
224			`if(rd = '0') then`
225			`iedcba <= "011011";`
226			`else`
227			`iedcba <= "100100";`
228			`end if;`
229			`when "11100" =>`
230			`temp_rd_s0 <= rd;`
231			`iedcba <= "011100";`
232			`when "11101" =>`
233			`temp_rd_s0 <= not rd;`
234			`if(rd = '0') then`
235			`iedcba <= "011101";`
236			`else`
237			`iedcba <= "100010";`
238			`end if;`
239			`when "11110" =>`
240			`temp_rd_s0 <= not rd;`
241			`if(rd = '0') then`
242			`iedcba <= "011110";`
243			`else`
244			`iedcba <= "100001";`
245			`end if;`
246			`when "11111" =>`
247			`temp_rd_s0 <= not rd;`
248			`if(rd = '0') then`
249			`iedcba <= "110101";`
250			`else`
251			`iedcba <= "001010";`
252			`end if;`
253			`when others =>`
254			`end case;`
255			`end process;`
256
257			`dxA <= '1' when (((EDCBA = 17 or EDCBA = 18 or EDCBA = 20) and temp_rd_s0 = '0') or`
258			`((EDCBA = 11 or EDCBA = 13 or EDCBA = 14) and temp_rd_s0 = '1'))`
259			`else '0';`
260
261			`process(HGF, EDCBA, dxA, temp_rd_s0)`
262			`begin`
263			`case HGF is`
264			`when "000" =>`
265			`temp_rd_k0 <= not temp_rd_s0;`
266			`if(temp_rd_s0 = '0') then`
267			`jhgf <= "1101";`
268			`else`
269			`jhgf <= "0010";`
270			`end if;`
271			`when "001" =>`
272			`temp_rd_k0 <= temp_rd_s0;`
273			`jhgf <= "1001";`
274			`when "010" =>`
275			`temp_rd_k0 <= temp_rd_s0;`
276			`jhgf <= "1010";`
277			`when "011" =>`
278			`temp_rd_k0 <= not temp_rd_s0;`
279			`if(temp_rd_s0 = '0') then`
280			`jhgf <= "0011";`
281			`else`
282			`jhgf <= "1100";`
283			`end if;`
284			`when "100" =>`
285			`temp_rd_k0 <= not temp_rd_s0;`
286			`if(temp_rd_s0 = '0') then`
287			`jhgf <= "1011";`
288			`else`
289			`jhgf <= "0100";`
290			`end if;`
291			`when "101" =>`
292			`temp_rd_k0 <= temp_rd_s0;`
293			`jhgf <= "0101";`
294			`when "110" =>`
295			`temp_rd_k0 <= temp_rd_s0;`
296			`jhgf <= "0110";`
297			`when "111" =>`
298			`temp_rd_k0 <= not temp_rd_s0;`
299			`if(dxA = '0') then`
300			`if(temp_rd_s0 = '0') then`
301			`jhgf <= "0111";`
302			`else`
303			`jhgf <= "1000";`
304			`end if;`
305			`else`
306			`if(temp_rd_s0 = '0') then`
307			`jhgf <= "1110";`
308			`else`
309			`jhgf <= "0001";`
310			`end if;`
311			`end if;`
312			`when others =>`
313			`end case;`
314			`end process;`
315
316
317
318
319			`end Behavioral;`
320