1 |
5 |
sonicwave |
------------------------------------------------------------------------------
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-- tosnet.vhd - entity/architecture pair
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------------------------------------------------------------------------------
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-- IMPORTANT:
|
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-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
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--
|
7 |
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-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
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--
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-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
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-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
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-- OF THE USER_LOGIC ENTITY.
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------------------------------------------------------------------------------
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--
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-- ***************************************************************************
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-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
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-- ** **
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-- ** Xilinx, Inc. **
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-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
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-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
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20 |
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-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
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-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
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-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
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-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
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-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
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-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
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-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
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-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
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-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
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-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
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-- ** FOR A PARTICULAR PURPOSE. **
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-- ** **
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-- ***************************************************************************
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--
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------------------------------------------------------------------------------
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-- Filename: tosnet.vhd
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-- Version: 3.20.a
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-- Description: Top level design, instantiates library components and user logic.
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-- Date: Tue Aug 03 15:27:10 2010 (by Create and Import Peripheral Wizard)
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-- VHDL Standard: VHDL'93
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------------------------------------------------------------------------------
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41 |
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-- Naming Conventions:
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-- active low signals: "*_n"
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-- clock signals: "clk", "clk_div#", "clk_#x"
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-- reset signals: "rst", "rst_n"
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-- generics: "C_*"
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-- user defined types: "*_TYPE"
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-- state machine next state: "*_ns"
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-- state machine current state: "*_cs"
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-- combinatorial signals: "*_com"
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-- pipelined or register delay signals: "*_d#"
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-- counter signals: "*cnt*"
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-- clock enable signals: "*_ce"
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-- internal version of output port: "*_i"
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-- device pins: "*_pin"
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-- ports: "- Names begin with Uppercase"
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-- processes: "*_PROCESS"
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-- component instantiations: "<ENTITY_>I_<#|FUNC>"
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library proc_common_v3_00_a;
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use proc_common_v3_00_a.proc_common_pkg.all;
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use proc_common_v3_00_a.ipif_pkg.all;
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library plbv46_slave_single_v1_01_a;
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use plbv46_slave_single_v1_01_a.plbv46_slave_single;
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library tosnet_v3_20_a;
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use tosnet_v3_20_a.user_logic;
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------------------------------------------------------------------------------
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-- Entity section
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------------------------------------------------------------------------------
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-- Definition of Generics:
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-- C_BASEADDR -- PLBv46 slave: base address
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-- C_HIGHADDR -- PLBv46 slave: high address
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-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
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-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
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-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
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-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
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-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
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-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
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-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
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88 |
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-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
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89 |
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-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
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90 |
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-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
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-- C_FAMILY -- Xilinx FPGA family
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92 |
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-- C_MEM0_BASEADDR -- User memory space 0 base address
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93 |
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-- C_MEM0_HIGHADDR -- User memory space 0 high address
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--
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-- Definition of Ports:
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-- SPLB_Clk -- PLB main bus clock
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97 |
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-- SPLB_Rst -- PLB main bus reset
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-- PLB_ABus -- PLB address bus
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-- PLB_UABus -- PLB upper address bus
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100 |
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-- PLB_PAValid -- PLB primary address valid indicator
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101 |
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-- PLB_SAValid -- PLB secondary address valid indicator
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102 |
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-- PLB_rdPrim -- PLB secondary to primary read request indicator
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103 |
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-- PLB_wrPrim -- PLB secondary to primary write request indicator
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104 |
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-- PLB_masterID -- PLB current master identifier
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105 |
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-- PLB_abort -- PLB abort request indicator
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106 |
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-- PLB_busLock -- PLB bus lock
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107 |
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-- PLB_RNW -- PLB read/not write
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108 |
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-- PLB_BE -- PLB byte enables
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109 |
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-- PLB_MSize -- PLB master data bus size
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110 |
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-- PLB_size -- PLB transfer size
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111 |
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-- PLB_type -- PLB transfer type
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112 |
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-- PLB_lockErr -- PLB lock error indicator
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113 |
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-- PLB_wrDBus -- PLB write data bus
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114 |
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-- PLB_wrBurst -- PLB burst write transfer indicator
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115 |
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-- PLB_rdBurst -- PLB burst read transfer indicator
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116 |
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-- PLB_wrPendReq -- PLB write pending bus request indicator
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117 |
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-- PLB_rdPendReq -- PLB read pending bus request indicator
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118 |
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-- PLB_wrPendPri -- PLB write pending request priority
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119 |
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-- PLB_rdPendPri -- PLB read pending request priority
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120 |
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-- PLB_reqPri -- PLB current request priority
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121 |
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-- PLB_TAttribute -- PLB transfer attribute
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122 |
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-- Sl_addrAck -- Slave address acknowledge
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123 |
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-- Sl_SSize -- Slave data bus size
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124 |
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-- Sl_wait -- Slave wait indicator
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125 |
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-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
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126 |
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-- Sl_wrDAck -- Slave write data acknowledge
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127 |
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-- Sl_wrComp -- Slave write transfer complete indicator
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128 |
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-- Sl_wrBTerm -- Slave terminate write burst transfer
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129 |
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-- Sl_rdDBus -- Slave read data bus
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130 |
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-- Sl_rdWdAddr -- Slave read word address
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131 |
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-- Sl_rdDAck -- Slave read data acknowledge
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132 |
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-- Sl_rdComp -- Slave read transfer complete indicator
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133 |
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-- Sl_rdBTerm -- Slave terminate read burst transfer
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134 |
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-- Sl_MBusy -- Slave busy indicator
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135 |
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-- Sl_MWrErr -- Slave write error indicator
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136 |
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-- Sl_MRdErr -- Slave read error indicator
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137 |
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-- Sl_MIRQ -- Slave interrupt indicator
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138 |
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|
------------------------------------------------------------------------------
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139 |
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|
140 |
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entity tosnet is
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141 |
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generic
|
142 |
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(
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143 |
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-- ADD USER GENERICS BELOW THIS LINE ---------------
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144 |
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C_REG_ENABLE : std_logic_vector(7 downto 0) := X"00";
|
145 |
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C_NODE_ID : integer := 0;
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146 |
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C_MAX_SKIPPED_READS : integer := 0;
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147 |
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C_MAX_SKIPPED_WRITES : integer := 0;
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148 |
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C_WATCHDOG_THRESHOLD : integer := 16384;
|
149 |
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C_DISABLE_MASTER : std_logic := '0';
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150 |
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C_DISABLE_SLAVE : std_logic := '0';
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151 |
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C_DISABLE_ASYNC : std_logic := '0';
|
152 |
|
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
|
153 |
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|
154 |
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-- DO NOT EDIT BELOW THIS LINE ---------------------
|
155 |
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-- Bus protocol parameters, do not add to or delete
|
156 |
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
|
157 |
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C_HIGHADDR : std_logic_vector := X"00000000";
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158 |
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C_SPLB_AWIDTH : integer := 32;
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159 |
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C_SPLB_DWIDTH : integer := 128;
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160 |
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C_SPLB_NUM_MASTERS : integer := 8;
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161 |
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C_SPLB_MID_WIDTH : integer := 3;
|
162 |
|
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C_SPLB_NATIVE_DWIDTH : integer := 32;
|
163 |
|
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C_SPLB_P2P : integer := 0;
|
164 |
|
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C_SPLB_SUPPORT_BURSTS : integer := 0;
|
165 |
|
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C_SPLB_SMALLEST_MASTER : integer := 32;
|
166 |
|
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C_SPLB_CLK_PERIOD_PS : integer := 10000;
|
167 |
|
|
C_INCLUDE_DPHASE_TIMER : integer := 0;
|
168 |
|
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C_FAMILY : string := "virtex5";
|
169 |
|
|
C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
|
170 |
|
|
C_MEM0_HIGHADDR : std_logic_vector := X"00000000"
|
171 |
|
|
-- DO NOT EDIT ABOVE THIS LINE ---------------------
|
172 |
|
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);
|
173 |
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|
port
|
174 |
|
|
(
|
175 |
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-- ADD USER PORTS BELOW THIS LINE ------------------
|
176 |
|
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sig_in : in std_logic;
|
177 |
|
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sig_out : out std_logic;
|
178 |
|
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clk_50M : in std_logic;
|
179 |
|
|
sync_strobe : out std_logic;
|
180 |
|
|
system_halt : out std_logic;
|
181 |
|
|
-- ADD USER PORTS ABOVE THIS LINE ------------------
|
182 |
|
|
|
183 |
|
|
-- DO NOT EDIT BELOW THIS LINE ---------------------
|
184 |
|
|
-- Bus protocol ports, do not add to or delete
|
185 |
|
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SPLB_Clk : in std_logic;
|
186 |
|
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SPLB_Rst : in std_logic;
|
187 |
|
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PLB_ABus : in std_logic_vector(0 to 31);
|
188 |
|
|
PLB_UABus : in std_logic_vector(0 to 31);
|
189 |
|
|
PLB_PAValid : in std_logic;
|
190 |
|
|
PLB_SAValid : in std_logic;
|
191 |
|
|
PLB_rdPrim : in std_logic;
|
192 |
|
|
PLB_wrPrim : in std_logic;
|
193 |
|
|
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
|
194 |
|
|
PLB_abort : in std_logic;
|
195 |
|
|
PLB_busLock : in std_logic;
|
196 |
|
|
PLB_RNW : in std_logic;
|
197 |
|
|
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
|
198 |
|
|
PLB_MSize : in std_logic_vector(0 to 1);
|
199 |
|
|
PLB_size : in std_logic_vector(0 to 3);
|
200 |
|
|
PLB_type : in std_logic_vector(0 to 2);
|
201 |
|
|
PLB_lockErr : in std_logic;
|
202 |
|
|
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
|
203 |
|
|
PLB_wrBurst : in std_logic;
|
204 |
|
|
PLB_rdBurst : in std_logic;
|
205 |
|
|
PLB_wrPendReq : in std_logic;
|
206 |
|
|
PLB_rdPendReq : in std_logic;
|
207 |
|
|
PLB_wrPendPri : in std_logic_vector(0 to 1);
|
208 |
|
|
PLB_rdPendPri : in std_logic_vector(0 to 1);
|
209 |
|
|
PLB_reqPri : in std_logic_vector(0 to 1);
|
210 |
|
|
PLB_TAttribute : in std_logic_vector(0 to 15);
|
211 |
|
|
Sl_addrAck : out std_logic;
|
212 |
|
|
Sl_SSize : out std_logic_vector(0 to 1);
|
213 |
|
|
Sl_wait : out std_logic;
|
214 |
|
|
Sl_rearbitrate : out std_logic;
|
215 |
|
|
Sl_wrDAck : out std_logic;
|
216 |
|
|
Sl_wrComp : out std_logic;
|
217 |
|
|
Sl_wrBTerm : out std_logic;
|
218 |
|
|
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
|
219 |
|
|
Sl_rdWdAddr : out std_logic_vector(0 to 3);
|
220 |
|
|
Sl_rdDAck : out std_logic;
|
221 |
|
|
Sl_rdComp : out std_logic;
|
222 |
|
|
Sl_rdBTerm : out std_logic;
|
223 |
|
|
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
|
224 |
|
|
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
|
225 |
|
|
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
|
226 |
|
|
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
|
227 |
|
|
-- DO NOT EDIT ABOVE THIS LINE ---------------------
|
228 |
|
|
);
|
229 |
|
|
|
230 |
|
|
attribute SIGIS : string;
|
231 |
|
|
attribute SIGIS of SPLB_Clk : signal is "CLK";
|
232 |
|
|
attribute SIGIS of SPLB_Rst : signal is "RST";
|
233 |
|
|
|
234 |
|
|
end entity tosnet;
|
235 |
|
|
|
236 |
|
|
------------------------------------------------------------------------------
|
237 |
|
|
-- Architecture section
|
238 |
|
|
------------------------------------------------------------------------------
|
239 |
|
|
|
240 |
|
|
architecture IMP of tosnet is
|
241 |
|
|
|
242 |
|
|
------------------------------------------
|
243 |
|
|
-- Array of base/high address pairs for each address range
|
244 |
|
|
------------------------------------------
|
245 |
|
|
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
|
246 |
|
|
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
|
247 |
|
|
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
|
248 |
|
|
|
249 |
|
|
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
|
250 |
|
|
(
|
251 |
|
|
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
|
252 |
|
|
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
|
253 |
|
|
ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address
|
254 |
|
|
ZERO_ADDR_PAD & C_MEM0_HIGHADDR -- user logic memory space 0 high address
|
255 |
|
|
);
|
256 |
|
|
|
257 |
|
|
------------------------------------------
|
258 |
|
|
-- Array of desired number of chip enables for each address range
|
259 |
|
|
------------------------------------------
|
260 |
|
|
constant USER_SLV_NUM_REG : integer := 5;
|
261 |
|
|
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
|
262 |
|
|
constant USER_NUM_MEM : integer := 1;
|
263 |
|
|
|
264 |
|
|
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
|
265 |
|
|
(
|
266 |
|
|
|
267 |
|
|
1 => 1 -- number of ce for user logic memory space 0 (always 1 chip enable)
|
268 |
|
|
);
|
269 |
|
|
|
270 |
|
|
------------------------------------------
|
271 |
|
|
-- Ratio of bus clock to core clock (for use in dual clock systems)
|
272 |
|
|
-- 1 = ratio is 1:1
|
273 |
|
|
-- 2 = ratio is 2:1
|
274 |
|
|
------------------------------------------
|
275 |
|
|
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
|
276 |
|
|
|
277 |
|
|
------------------------------------------
|
278 |
|
|
-- Width of the slave data bus (32 only)
|
279 |
|
|
------------------------------------------
|
280 |
|
|
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
|
281 |
|
|
|
282 |
|
|
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
|
283 |
|
|
|
284 |
|
|
------------------------------------------
|
285 |
|
|
-- Width of the slave address bus (32 only)
|
286 |
|
|
------------------------------------------
|
287 |
|
|
constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
|
288 |
|
|
|
289 |
|
|
------------------------------------------
|
290 |
|
|
-- Index for CS/CE
|
291 |
|
|
------------------------------------------
|
292 |
|
|
constant USER_SLV_CS_INDEX : integer := 0;
|
293 |
|
|
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
|
294 |
|
|
constant USER_MEM0_CS_INDEX : integer := 1;
|
295 |
|
|
constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
|
296 |
|
|
|
297 |
|
|
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
|
298 |
|
|
|
299 |
|
|
------------------------------------------
|
300 |
|
|
-- IP Interconnect (IPIC) signal declarations
|
301 |
|
|
------------------------------------------
|
302 |
|
|
signal ipif_Bus2IP_Clk : std_logic;
|
303 |
|
|
signal ipif_Bus2IP_Reset : std_logic;
|
304 |
|
|
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
|
305 |
|
|
signal ipif_IP2Bus_WrAck : std_logic;
|
306 |
|
|
signal ipif_IP2Bus_RdAck : std_logic;
|
307 |
|
|
signal ipif_IP2Bus_Error : std_logic;
|
308 |
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signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
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signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
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signal ipif_Bus2IP_RNW : std_logic;
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signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
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signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
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signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
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signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
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signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
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signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
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signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
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signal user_IP2Bus_RdAck : std_logic;
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signal user_IP2Bus_WrAck : std_logic;
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signal user_IP2Bus_Error : std_logic;
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begin
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------------------------------------------
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-- instantiate plbv46_slave_single
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------------------------------------------
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PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
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generic map
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(
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C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
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C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
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C_SPLB_P2P => C_SPLB_P2P,
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C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
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C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
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C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
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C_SPLB_AWIDTH => C_SPLB_AWIDTH,
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C_SPLB_DWIDTH => C_SPLB_DWIDTH,
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C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
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C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
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C_FAMILY => C_FAMILY
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)
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port map
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(
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SPLB_Clk => SPLB_Clk,
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SPLB_Rst => SPLB_Rst,
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PLB_ABus => PLB_ABus,
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PLB_UABus => PLB_UABus,
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PLB_PAValid => PLB_PAValid,
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PLB_SAValid => PLB_SAValid,
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PLB_rdPrim => PLB_rdPrim,
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PLB_wrPrim => PLB_wrPrim,
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PLB_masterID => PLB_masterID,
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PLB_abort => PLB_abort,
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PLB_busLock => PLB_busLock,
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PLB_RNW => PLB_RNW,
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PLB_BE => PLB_BE,
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PLB_MSize => PLB_MSize,
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PLB_size => PLB_size,
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PLB_type => PLB_type,
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PLB_lockErr => PLB_lockErr,
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PLB_wrDBus => PLB_wrDBus,
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PLB_wrBurst => PLB_wrBurst,
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363 |
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PLB_rdBurst => PLB_rdBurst,
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364 |
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PLB_wrPendReq => PLB_wrPendReq,
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PLB_rdPendReq => PLB_rdPendReq,
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PLB_wrPendPri => PLB_wrPendPri,
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PLB_rdPendPri => PLB_rdPendPri,
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PLB_reqPri => PLB_reqPri,
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PLB_TAttribute => PLB_TAttribute,
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Sl_addrAck => Sl_addrAck,
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Sl_SSize => Sl_SSize,
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Sl_wait => Sl_wait,
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Sl_rearbitrate => Sl_rearbitrate,
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Sl_wrDAck => Sl_wrDAck,
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Sl_wrComp => Sl_wrComp,
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Sl_wrBTerm => Sl_wrBTerm,
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Sl_rdDBus => Sl_rdDBus,
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Sl_rdWdAddr => Sl_rdWdAddr,
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379 |
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Sl_rdDAck => Sl_rdDAck,
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380 |
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Sl_rdComp => Sl_rdComp,
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381 |
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Sl_rdBTerm => Sl_rdBTerm,
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382 |
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Sl_MBusy => Sl_MBusy,
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383 |
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Sl_MWrErr => Sl_MWrErr,
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384 |
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Sl_MRdErr => Sl_MRdErr,
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385 |
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Sl_MIRQ => Sl_MIRQ,
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386 |
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Bus2IP_Clk => ipif_Bus2IP_Clk,
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387 |
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Bus2IP_Reset => ipif_Bus2IP_Reset,
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388 |
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IP2Bus_Data => ipif_IP2Bus_Data,
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389 |
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IP2Bus_WrAck => ipif_IP2Bus_WrAck,
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390 |
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IP2Bus_RdAck => ipif_IP2Bus_RdAck,
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391 |
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IP2Bus_Error => ipif_IP2Bus_Error,
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392 |
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Bus2IP_Addr => ipif_Bus2IP_Addr,
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393 |
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Bus2IP_Data => ipif_Bus2IP_Data,
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394 |
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Bus2IP_RNW => ipif_Bus2IP_RNW,
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395 |
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Bus2IP_BE => ipif_Bus2IP_BE,
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396 |
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Bus2IP_CS => ipif_Bus2IP_CS,
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397 |
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Bus2IP_RdCE => ipif_Bus2IP_RdCE,
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398 |
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Bus2IP_WrCE => ipif_Bus2IP_WrCE
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399 |
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);
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400 |
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401 |
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------------------------------------------
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402 |
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-- instantiate User Logic
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403 |
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------------------------------------------
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404 |
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USER_LOGIC_I : entity tosnet_v3_20_a.user_logic
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405 |
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generic map
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406 |
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(
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407 |
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-- MAP USER GENERICS BELOW THIS LINE ---------------
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408 |
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C_REG_ENABLE => C_REG_ENABLE,
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409 |
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C_NODE_ID => C_NODE_ID,
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410 |
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C_MAX_SKIPPED_READS => C_MAX_SKIPPED_READS,
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411 |
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C_MAX_SKIPPED_WRITES => C_MAX_SKIPPED_WRITES,
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412 |
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C_WATCHDOG_THRESHOLD => C_WATCHDOG_THRESHOLD,
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413 |
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C_DISABLE_MASTER => C_DISABLE_MASTER,
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414 |
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C_DISABLE_SLAVE => C_DISABLE_SLAVE,
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415 |
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C_DISABLE_ASYNC => C_DISABLE_ASYNC,
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416 |
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-- MAP USER GENERICS ABOVE THIS LINE ---------------
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417 |
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418 |
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C_SLV_AWIDTH => USER_SLV_AWIDTH,
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419 |
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C_SLV_DWIDTH => USER_SLV_DWIDTH,
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420 |
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C_NUM_REG => USER_NUM_REG,
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421 |
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C_NUM_MEM => USER_NUM_MEM
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422 |
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)
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423 |
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port map
|
424 |
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(
|
425 |
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-- MAP USER PORTS BELOW THIS LINE ------------------
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426 |
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sig_in => sig_in,
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427 |
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sig_out => sig_out,
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428 |
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clk_50M => clk_50M,
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429 |
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sync_strobe => sync_strobe,
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430 |
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system_halt => system_halt,
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431 |
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-- MAP USER PORTS ABOVE THIS LINE ------------------
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432 |
|
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433 |
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Bus2IP_Clk => ipif_Bus2IP_Clk,
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434 |
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Bus2IP_Reset => ipif_Bus2IP_Reset,
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435 |
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Bus2IP_Addr => ipif_Bus2IP_Addr,
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436 |
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Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
|
437 |
|
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Bus2IP_RNW => ipif_Bus2IP_RNW,
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438 |
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Bus2IP_Data => ipif_Bus2IP_Data,
|
439 |
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Bus2IP_BE => ipif_Bus2IP_BE,
|
440 |
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Bus2IP_RdCE => user_Bus2IP_RdCE,
|
441 |
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Bus2IP_WrCE => user_Bus2IP_WrCE,
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442 |
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IP2Bus_Data => user_IP2Bus_Data,
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443 |
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IP2Bus_RdAck => user_IP2Bus_RdAck,
|
444 |
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IP2Bus_WrAck => user_IP2Bus_WrAck,
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445 |
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IP2Bus_Error => user_IP2Bus_Error
|
446 |
|
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);
|
447 |
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|
448 |
|
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------------------------------------------
|
449 |
|
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-- connect internal signals
|
450 |
|
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------------------------------------------
|
451 |
|
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IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
|
452 |
|
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begin
|
453 |
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|
454 |
|
|
case ipif_Bus2IP_CS is
|
455 |
|
|
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
|
456 |
|
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when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
|
457 |
|
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when others => ipif_IP2Bus_Data <= (others => '0');
|
458 |
|
|
end case;
|
459 |
|
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|
460 |
|
|
end process IP2BUS_DATA_MUX_PROC;
|
461 |
|
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|
462 |
|
|
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
|
463 |
|
|
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
|
464 |
|
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ipif_IP2Bus_Error <= user_IP2Bus_Error;
|
465 |
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|
466 |
|
|
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
|
467 |
|
|
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
|
468 |
|
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|
469 |
|
|
end IMP;
|