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[/] [tosnet/] [trunk/] [gateware/] [MicroBlaze_Peripheral_rev3_2/] [pcores/] [tosnet_v3_20_a/] [hdl/] [vhdl/] [tpl_tx.vhd] - Blame information for rev 5

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----------------------------------------------------------------------------------
-- Company:             University of Southern Denmark
-- Engineer:            Simon Falsig
-- 
-- Create Date:         12/3/2009 
-- Design Name:         TosNet
-- Module Name:         tdl_tx - Behavioral 
-- File Name:           tdl_tx.vhd
-- Project Name:        TosNet
-- Target Devices:      Spartan3/6
-- Tool versions:       Xilinx ISE 12.2
-- Description:         The transmit part of the TosNet physical layer.
--
-- Revision: 
-- Revision 3.2 -       Initial release
--
-- Copyright 2010
--
-- This module is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This module is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this module.  If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity tpl_tx is
        Port (  data                            : in    STD_LOGIC_VECTOR(7 downto 0);
                        clk_50M                         : in    STD_LOGIC;
                        clk_data_en                     : out   STD_LOGIC;
                        enable                          : in    STD_LOGIC;
                        reset                           : in    STD_LOGIC;
                        sig_out                         : out   STD_LOGIC;
                        clk_div_reset           : in    STD_LOGIC;
                        clk_div_reset_ack       : out   STD_LOGIC);
end tpl_tx;
 
architecture Behavioral of tpl_tx is
 
        constant LFSR_INITIAL_SEED      : STD_LOGIC_VECTOR(7 downto 0) := "01010101";
        constant K_COMMA_1                      : STD_LOGIC_VECTOR(7 downto 0) := "00111100";
        constant K_COMMA_2                      : STD_LOGIC_VECTOR(7 downto 0) := "10111100";
 
        signal last_clk_div_reset       : STD_LOGIC;
        signal reset_clk_div            : STD_LOGIC := '0';
        signal clk_div                          : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
        signal clk_en_12M5                      : STD_LOGIC;
 
        signal clk_en_1M25_0            : STD_LOGIC;
        signal clk_en_1M25_1            : STD_LOGIC;
        signal clk_en_1M25_2            : STD_LOGIC;
        signal clk_en_1M25_3            : STD_LOGIC;
 
        signal data_buffer_1            : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
        signal data_buffer_2            : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
        signal data_buffer_3            : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
        signal enable_buffer_1          : STD_LOGIC := '0';
        signal enable_buffer_2          : STD_LOGIC := '0';
 
        signal out_buffer                       : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
 
        type STATES is (IDLE, TRN_START, TRN_SEED, TRN_DATA);
 
        signal state                            : STATES := IDLE;
        signal next_state                       : STATES := IDLE;
 
        signal lfsr_seed_out            : STD_LOGIC_VECTOR(7 downto 0);
        signal lfsr_seed_seed           : STD_LOGIC_VECTOR(7 downto 0);
        signal lfsr_seed_reset          : STD_LOGIC;
        signal lfsr_seed_clk            : STD_LOGIC;
        signal lfsr_seed_clk_en         : STD_LOGIC;
 
        signal lfsr_trn_out                     : STD_LOGIC_VECTOR(7 downto 0);
        signal lfsr_trn_seed            : STD_LOGIC_VECTOR(7 downto 0);
        signal lfsr_trn_reset           : STD_LOGIC;
        signal lfsr_trn_clk                     : STD_LOGIC;
        signal lfsr_trn_clk_en          : STD_LOGIC;
 
        signal enc_in                           : STD_LOGIC_VECTOR(7 downto 0) := K_COMMA_1;
        signal enc_out                          : STD_LOGIC_VECTOR(9 downto 0);
        signal enc_kin                          : STD_LOGIC := '1';
        signal enc_clk                          : STD_LOGIC;
        signal enc_clk_en                       : STD_LOGIC;
 
        component lfsr is
                generic (
                        lfsr_length             : STD_LOGIC_VECTOR(7 downto 0);
                        lfsr_out_length         : STD_LOGIC_VECTOR(7 downto 0);
                        lfsr_allow_zero         : STD_LOGIC);
                port (
                        lfsr_out                        : out   STD_LOGIC_VECTOR((conv_integer(lfsr_out_length) - 1) downto 0);
                        lfsr_seed                       : in    STD_LOGIC_VECTOR((conv_integer(lfsr_length) - 1) downto 0);
                        lfsr_reset                      : in    STD_LOGIC;
                        lfsr_clk                        : in    STD_LOGIC;
                        lfsr_clk_en                     : in    STD_LOGIC);
        end component;
 
        component enc_8b10b is
                port (
                        din                                     : in    STD_LOGIC_VECTOR(7 downto 0);
                        kin                                     : in    STD_LOGIC;
                        clk                                     : in    STD_LOGIC;
                        dout                            : out   STD_LOGIC_VECTOR(9 downto 0);
                        ce                                      : in    STD_LOGIC);
        end component;
 
begin
 
        clk_data_en <= clk_en_1M25_0;
 
        lfsr_seed_seed <= LFSR_INITIAL_SEED;
        lfsr_seed_clk <= clk_50M;
        lfsr_seed_reset <= reset;
 
        lfsr_trn_clk <= clk_50M;
        lfsr_trn_clk_en <= clk_en_1M25_1;
 
        lfsr_seed : lfsr
        Generic map (   lfsr_length => "00001000",
                                        lfsr_out_length => "00001000",
                                        lfsr_allow_zero => '0')
        Port map (              lfsr_out => lfsr_seed_out,
                                        lfsr_seed => lfsr_seed_seed,
                                        lfsr_reset => lfsr_seed_reset,
                                        lfsr_clk => lfsr_seed_clk,
                                        lfsr_clk_en => lfsr_seed_clk_en);
 
        lfsr_trn : lfsr
        Generic map (   lfsr_length => "00001000",
                                        lfsr_out_length => "00001000",
                                        lfsr_allow_zero => '0')
        Port map (              lfsr_out => lfsr_trn_out,
                                        lfsr_seed => lfsr_trn_seed,
                                        lfsr_reset => lfsr_trn_reset,
                                        lfsr_clk => lfsr_trn_clk,
                                        lfsr_clk_en => lfsr_trn_clk_en);
 
        enc : enc_8b10b
        Port map (              din => enc_in,
                                        kin => enc_kin,
                                        clk => enc_clk,
                                        dout => enc_out,
                                        ce => enc_clk_en);
 
        enc_clk <=  clk_50M;
        enc_clk_en <= clk_en_1M25_2;
 
        process(clk_50M)
        begin
                if(clk_50M = '1' and clk_50M'event) then
                        if(clk_div_reset = '1' and last_clk_div_reset = '0') then
                                reset_clk_div <= '1';
                        elsif(clk_div_reset = '0') then
                                clk_div_reset_ack <= '0';
                        end if;
 
                        if(reset_clk_div = '1' and clk_div(1 downto 0) = "11") then
                                clk_div <= "100100";
                                reset_clk_div <= '0';
                                clk_div_reset_ack <= '1';
                        else
                                if(clk_div = 39) then
                                        clk_div <= (others => '0');
                                else
                                        clk_div <= clk_div + 1;
                                end if;
                        end if;
 
                        last_clk_div_reset <= clk_div_reset;
                end if;
        end process;
 
        clk_en_12M5 <= '1' when clk_div(1 downto 0) = "11" else '0';                      --Sync the phase to clk_en_1M25_3
        clk_en_1M25_0 <= '1' when clk_div = "000000" else '0';                                   --We're using phase-shifted versions of the clock-enables to minimize the latency of the system, as all the parts are perfectly pipelined anyway
        clk_en_1M25_1 <= '1' when clk_div = "000001" else '0';
        clk_en_1M25_2 <= '1' when clk_div = "000010" else '0';
        clk_en_1M25_3 <= '1' when clk_div = "000011" else '0';
 
        lfsr_trn_seed <= lfsr_seed_out;
 
        process(clk_50M)
        begin
                if(clk_50M = '1' and clk_50M'event) then
                        if(reset = '1') then
                                state <= IDLE;
                        elsif(clk_en_1M25_1 = '1') then
                                state <= next_state;
 
                                data_buffer_3 <= data_buffer_2;
                                data_buffer_2 <= data_buffer_1;
                                data_buffer_1 <= data;
 
                                enable_buffer_2 <= enable_buffer_1;
                                enable_buffer_1 <= enable;
                        end if;
                end if;
        end process;
 
        process(state, lfsr_trn_seed, data_buffer_3, lfsr_trn_out, clk_en_1M25_1)
        begin
                case state is
                        when IDLE =>
                                enc_in <= K_COMMA_1;
                                enc_kin <= '1';
                                lfsr_trn_reset <= '1';
                                lfsr_seed_clk_en <= clk_en_1M25_1;
                        when TRN_START =>
                                enc_in <= K_COMMA_2;
                                enc_kin <= '1';
                                lfsr_trn_reset <= '1';
                                lfsr_seed_clk_en <= '0';
                        when TRN_SEED =>
                                enc_in <= lfsr_trn_seed;
                                enc_kin <= '0';
                                lfsr_trn_reset <= '0';
                                lfsr_seed_clk_en <= '0';
                        when TRN_DATA =>
                                enc_in <= data_buffer_3 xor lfsr_trn_out;
                                enc_kin <= '0';
                                lfsr_trn_reset <= '0';
                                lfsr_seed_clk_en <= '0';
                end case;
        end process;
 
 
        process(clk_50M)
        begin
                if(clk_50M = '1' and clk_50M'event) then
                        if(reset = '1') then
                                out_buffer <= (others => '0');
                                sig_out <= '0';
                        elsif(clk_en_12M5 = '1') then
                                if(clk_en_1M25_3 = '1') then
                                        out_buffer <= enc_out;
                                else
                                        out_buffer <= '0' & out_buffer(9 downto 1);
                                end if;
 
                                sig_out <= out_buffer(0);
                        end if;
                end if;
        end process;
 
 
 
        process(state, enable, enable_buffer_2)
        begin
                case state is
                        when IDLE =>
                                if(enable = '1') then
                                        next_state <= TRN_START;
                                else
                                        next_state <= IDLE;
                                end if;
                        when TRN_START =>
                                next_state <= TRN_SEED;
                        when TRN_SEED =>
                                next_state <= TRN_DATA;
                        when TRN_DATA =>
                                if(enable_buffer_2 = '1') then
                                        next_state <= TRN_DATA;
                                else
                                        next_state <= IDLE;
                                end if;
                end case;
        end process;
 
 
end Behavioral;

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[/] [tosnet/] [trunk/] [gateware/] [MicroBlaze_Peripheral_rev3_2/] [pcores/] [tosnet_v3_20_a/] [hdl/] [vhdl/] [tpl_tx.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	sonicwave	`----------------------------------------------------------------------------------`
2			`-- Company: University of Southern Denmark`
3			`-- Engineer: Simon Falsig`
4			`--`
5			`-- Create Date: 12/3/2009`
6			`-- Design Name: TosNet`
7			`-- Module Name: tdl_tx - Behavioral`
8			`-- File Name: tdl_tx.vhd`
9			`-- Project Name: TosNet`
10			`-- Target Devices: Spartan3/6`
11			`-- Tool versions: Xilinx ISE 12.2`
12			`-- Description: The transmit part of the TosNet physical layer.`
13			`--`
14			`-- Revision:`
15			`-- Revision 3.2 - Initial release`
16			`--`
17			`-- Copyright 2010`
18			`--`
19			`-- This module is free software: you can redistribute it and/or modify`
20			`-- it under the terms of the GNU Lesser General Public License as published by`
21			`-- the Free Software Foundation, either version 3 of the License, or`
22			`-- (at your option) any later version.`
23			`--`
24			`-- This module is distributed in the hope that it will be useful,`
25			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
26			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
27			`-- GNU Lesser General Public License for more details.`
28			`--`
29			`-- You should have received a copy of the GNU Lesser General Public License`
30			`-- along with this module. If not, see <http://www.gnu.org/licenses/>.`
31			`--------------------------------------------------------------------------------------------------------------------------------------------------------------------`
32			`library IEEE;`
33			`use IEEE.STD_LOGIC_1164.ALL;`
34			`use IEEE.STD_LOGIC_ARITH.ALL;`
35			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
36
37
38			`entity tpl_tx is`
39			`Port ( data : in STD_LOGIC_VECTOR(7 downto 0);`
40			`clk_50M : in STD_LOGIC;`
41			`clk_data_en : out STD_LOGIC;`
42			`enable : in STD_LOGIC;`
43			`reset : in STD_LOGIC;`
44			`sig_out : out STD_LOGIC;`
45			`clk_div_reset : in STD_LOGIC;`
46			`clk_div_reset_ack : out STD_LOGIC);`
47			`end tpl_tx;`
48
49			`architecture Behavioral of tpl_tx is`
50
51			`constant LFSR_INITIAL_SEED : STD_LOGIC_VECTOR(7 downto 0) := "01010101";`
52			`constant K_COMMA_1 : STD_LOGIC_VECTOR(7 downto 0) := "00111100";`
53			`constant K_COMMA_2 : STD_LOGIC_VECTOR(7 downto 0) := "10111100";`
54
55			`signal last_clk_div_reset : STD_LOGIC;`
56			`signal reset_clk_div : STD_LOGIC := '0';`
57			`signal clk_div : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');`
58			`signal clk_en_12M5 : STD_LOGIC;`
59
60			`signal clk_en_1M25_0 : STD_LOGIC;`
61			`signal clk_en_1M25_1 : STD_LOGIC;`
62			`signal clk_en_1M25_2 : STD_LOGIC;`
63			`signal clk_en_1M25_3 : STD_LOGIC;`
64
65			`signal data_buffer_1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');`
66			`signal data_buffer_2 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');`
67			`signal data_buffer_3 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');`
68			`signal enable_buffer_1 : STD_LOGIC := '0';`
69			`signal enable_buffer_2 : STD_LOGIC := '0';`
70
71			`signal out_buffer : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');`
72
73			`type STATES is (IDLE, TRN_START, TRN_SEED, TRN_DATA);`
74
75			`signal state : STATES := IDLE;`
76			`signal next_state : STATES := IDLE;`
77
78			`signal lfsr_seed_out : STD_LOGIC_VECTOR(7 downto 0);`
79			`signal lfsr_seed_seed : STD_LOGIC_VECTOR(7 downto 0);`
80			`signal lfsr_seed_reset : STD_LOGIC;`
81			`signal lfsr_seed_clk : STD_LOGIC;`
82			`signal lfsr_seed_clk_en : STD_LOGIC;`
83
84			`signal lfsr_trn_out : STD_LOGIC_VECTOR(7 downto 0);`
85			`signal lfsr_trn_seed : STD_LOGIC_VECTOR(7 downto 0);`
86			`signal lfsr_trn_reset : STD_LOGIC;`
87			`signal lfsr_trn_clk : STD_LOGIC;`
88			`signal lfsr_trn_clk_en : STD_LOGIC;`
89
90			`signal enc_in : STD_LOGIC_VECTOR(7 downto 0) := K_COMMA_1;`
91			`signal enc_out : STD_LOGIC_VECTOR(9 downto 0);`
92			`signal enc_kin : STD_LOGIC := '1';`
93			`signal enc_clk : STD_LOGIC;`
94			`signal enc_clk_en : STD_LOGIC;`
95
96			`component lfsr is`
97			`generic (`
98			`lfsr_length : STD_LOGIC_VECTOR(7 downto 0);`
99			`lfsr_out_length : STD_LOGIC_VECTOR(7 downto 0);`
100			`lfsr_allow_zero : STD_LOGIC);`
101			`port (`
102			`lfsr_out : out STD_LOGIC_VECTOR((conv_integer(lfsr_out_length) - 1) downto 0);`
103			`lfsr_seed : in STD_LOGIC_VECTOR((conv_integer(lfsr_length) - 1) downto 0);`
104			`lfsr_reset : in STD_LOGIC;`
105			`lfsr_clk : in STD_LOGIC;`
106			`lfsr_clk_en : in STD_LOGIC);`
107			`end component;`
108
109			`component enc_8b10b is`
110			`port (`
111			`din : in STD_LOGIC_VECTOR(7 downto 0);`
112			`kin : in STD_LOGIC;`
113			`clk : in STD_LOGIC;`
114			`dout : out STD_LOGIC_VECTOR(9 downto 0);`
115			`ce : in STD_LOGIC);`
116			`end component;`
117
118			`begin`
119
120			`clk_data_en <= clk_en_1M25_0;`
121
122			`lfsr_seed_seed <= LFSR_INITIAL_SEED;`
123			`lfsr_seed_clk <= clk_50M;`
124			`lfsr_seed_reset <= reset;`
125
126			`lfsr_trn_clk <= clk_50M;`
127			`lfsr_trn_clk_en <= clk_en_1M25_1;`
128
129			`lfsr_seed : lfsr`
130			`Generic map ( lfsr_length => "00001000",`
131			`lfsr_out_length => "00001000",`
132			`lfsr_allow_zero => '0')`
133			`Port map ( lfsr_out => lfsr_seed_out,`
134			`lfsr_seed => lfsr_seed_seed,`
135			`lfsr_reset => lfsr_seed_reset,`
136			`lfsr_clk => lfsr_seed_clk,`
137			`lfsr_clk_en => lfsr_seed_clk_en);`
138
139			`lfsr_trn : lfsr`
140			`Generic map ( lfsr_length => "00001000",`
141			`lfsr_out_length => "00001000",`
142			`lfsr_allow_zero => '0')`
143			`Port map ( lfsr_out => lfsr_trn_out,`
144			`lfsr_seed => lfsr_trn_seed,`
145			`lfsr_reset => lfsr_trn_reset,`
146			`lfsr_clk => lfsr_trn_clk,`
147			`lfsr_clk_en => lfsr_trn_clk_en);`
148
149			`enc : enc_8b10b`
150			`Port map ( din => enc_in,`
151			`kin => enc_kin,`
152			`clk => enc_clk,`
153			`dout => enc_out,`
154			`ce => enc_clk_en);`
155
156			`enc_clk <= clk_50M;`
157			`enc_clk_en <= clk_en_1M25_2;`
158
159			`process(clk_50M)`
160			`begin`
161			`if(clk_50M = '1' and clk_50M'event) then`
162			`if(clk_div_reset = '1' and last_clk_div_reset = '0') then`
163			`reset_clk_div <= '1';`
164			`elsif(clk_div_reset = '0') then`
165			`clk_div_reset_ack <= '0';`
166			`end if;`
167
168			`if(reset_clk_div = '1' and clk_div(1 downto 0) = "11") then`
169			`clk_div <= "100100";`
170			`reset_clk_div <= '0';`
171			`clk_div_reset_ack <= '1';`
172			`else`
173			`if(clk_div = 39) then`
174			`clk_div <= (others => '0');`
175			`else`
176			`clk_div <= clk_div + 1;`
177			`end if;`
178			`end if;`
179
180			`last_clk_div_reset <= clk_div_reset;`
181			`end if;`
182			`end process;`
183
184			`clk_en_12M5 <= '1' when clk_div(1 downto 0) = "11" else '0'; --Sync the phase to clk_en_1M25_3`
185			`clk_en_1M25_0 <= '1' when clk_div = "000000" else '0'; --We're using phase-shifted versions of the clock-enables to minimize the latency of the system, as all the parts are perfectly pipelined anyway`
186			`clk_en_1M25_1 <= '1' when clk_div = "000001" else '0';`
187			`clk_en_1M25_2 <= '1' when clk_div = "000010" else '0';`
188			`clk_en_1M25_3 <= '1' when clk_div = "000011" else '0';`
189
190			`lfsr_trn_seed <= lfsr_seed_out;`
191
192			`process(clk_50M)`
193			`begin`
194			`if(clk_50M = '1' and clk_50M'event) then`
195			`if(reset = '1') then`
196			`state <= IDLE;`
197			`elsif(clk_en_1M25_1 = '1') then`
198			`state <= next_state;`
199
200			`data_buffer_3 <= data_buffer_2;`
201			`data_buffer_2 <= data_buffer_1;`
202			`data_buffer_1 <= data;`
203
204			`enable_buffer_2 <= enable_buffer_1;`
205			`enable_buffer_1 <= enable;`
206			`end if;`
207			`end if;`
208			`end process;`
209
210			`process(state, lfsr_trn_seed, data_buffer_3, lfsr_trn_out, clk_en_1M25_1)`
211			`begin`
212			`case state is`
213			`when IDLE =>`
214			`enc_in <= K_COMMA_1;`
215			`enc_kin <= '1';`
216			`lfsr_trn_reset <= '1';`
217			`lfsr_seed_clk_en <= clk_en_1M25_1;`
218			`when TRN_START =>`
219			`enc_in <= K_COMMA_2;`
220			`enc_kin <= '1';`
221			`lfsr_trn_reset <= '1';`
222			`lfsr_seed_clk_en <= '0';`
223			`when TRN_SEED =>`
224			`enc_in <= lfsr_trn_seed;`
225			`enc_kin <= '0';`
226			`lfsr_trn_reset <= '0';`
227			`lfsr_seed_clk_en <= '0';`
228			`when TRN_DATA =>`
229			`enc_in <= data_buffer_3 xor lfsr_trn_out;`
230			`enc_kin <= '0';`
231			`lfsr_trn_reset <= '0';`
232			`lfsr_seed_clk_en <= '0';`
233			`end case;`
234			`end process;`
235
236
237			`process(clk_50M)`
238			`begin`
239			`if(clk_50M = '1' and clk_50M'event) then`
240			`if(reset = '1') then`
241			`out_buffer <= (others => '0');`
242			`sig_out <= '0';`
243			`elsif(clk_en_12M5 = '1') then`
244			`if(clk_en_1M25_3 = '1') then`
245			`out_buffer <= enc_out;`
246			`else`
247			`out_buffer <= '0' & out_buffer(9 downto 1);`
248			`end if;`
249
250			`sig_out <= out_buffer(0);`
251			`end if;`
252			`end if;`
253			`end process;`
254
255
256
257			`process(state, enable, enable_buffer_2)`
258			`begin`
259			`case state is`
260			`when IDLE =>`
261			`if(enable = '1') then`
262			`next_state <= TRN_START;`
263			`else`
264			`next_state <= IDLE;`
265			`end if;`
266			`when TRN_START =>`
267			`next_state <= TRN_SEED;`
268			`when TRN_SEED =>`
269			`next_state <= TRN_DATA;`
270			`when TRN_DATA =>`
271			`if(enable_buffer_2 = '1') then`
272			`next_state <= TRN_DATA;`
273			`else`
274			`next_state <= IDLE;`
275			`end if;`
276			`end case;`
277			`end process;`
278
279
280			`end Behavioral;`