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[/] [turbo8051/] [trunk/] [verif/] [log/] [int_fib.log] - Blame information for rev 74

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Line No. Rev Author Line
1 74 dinesha
Reading /mtitcl/vsim/pref.tcl
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# 10.2b
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# vsim +INTERNAL_ROM -do run.do -c tb_top
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# //  Questa Sim-64
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# //  Version 10.2b linux_x86_64 May 16 2013
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# //
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# //  Copyright 1991-2013 Mentor Graphics Corporation
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# //  All Rights Reserved.
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# //
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# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
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# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
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# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
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# //
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# Loading sv_std.std
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# Loading work.tb_top(fast)
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# Loading work.oc8051_top(fast)
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# Loading work.tb_eth_top(fast)
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# Loading work.AT45DB321(fast)
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# do run.do
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# i : 02
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# i : 00
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# i : 08
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# i : 12
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# i : 01
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# i : 51
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# i : 80
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# i : fe
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# i : 75
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# i : 81
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# NOTE : Load memory with Initial delivery content
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# NOTE : Initial Load End
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# NOTE: COMMUNICATION (RE)STARTED
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################################
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# time                62216 Passed
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################################
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# ** Note: $finish    : ../tb/tb_top.v(448)
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#    Time: 62316 ns  Iteration: 0  Instance: /tb_top

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