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dbrochart |
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#### ####
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#### clock.py ####
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#### ####
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#### This file is part of the turbo decoder IP core project ####
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#### http://www.opencores.org/projects/turbocodes/ ####
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#### ####
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#### Author(s): ####
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#### - David Brochart(dbrochart@opencores.org) ####
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#### ####
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#### All additional information is available in the README.txt ####
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#### file. ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2005 Authors ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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from myhdl import Signal, delay, posedge, negedge, instance, always
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def clkGen(clk, duration_1 = 10, duration_2 = 10):
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""" Clock signal generator.
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duration_1 -- first level duration
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duration_2 -- second level duration
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clk -- out : generated clock signal
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"""
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@instance
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def clkGenLogic():
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while 1:
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yield delay(duration_1)
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clk.next = not clk.val
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yield delay(duration_2)
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clk.next = not clk.val
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return clkGenLogic
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def rstGen(rst, start = 5, duration = 10):
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""" Reset signal generator.
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start -- reset pulse start time
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duration -- reset pulse duration
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rst -- out : generated reset signal
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"""
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@instance
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def rstGenLogic():
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yield delay(start)
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rst.next = not rst.val
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yield delay(duration)
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rst.next = not rst.val
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return rstGenLogic
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def clkDiv(clk, rst, clkout):
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""" Clock divider (freq/2).
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clk, rst -- in : clock and negative reset
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clkout -- out : clock which frequency is half of the input clock
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"""
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@always(clk.posedge, rst.negedge)
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def clkDivLogic():
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if rst.val == 0:
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clkout.next = False
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else:
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clkout.next = not clkout.val
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return clkDivLogic
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