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dbrochart |
######################################################################
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#### ####
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#### misc.py ####
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#### ####
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#### This file is part of the turbo decoder IP core project ####
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#### http://www.opencores.org/projects/turbocodes/ ####
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#### ####
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#### Author(s): ####
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#### - David Brochart(dbrochart@opencores.org) ####
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#### ####
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#### All additional information is available in the README.txt ####
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#### file. ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2005 Authors ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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from myhdl import Signal, intbv, always_comb, instance, always, posedge, negedge, concat
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def delayer(clk, rst, d, q, delay = 1, mi = 0, ma = 1):
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""" Delayer.
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delay -- number of clock cycles to delay
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mi -- minimum value of the signal to delay
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ma -- maximum value of the signal to delay
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clk, rst -- in : clock and negative reset
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d -- in : signal to be delayed by "delay" clock cycles
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q -- out : delayed signal
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"""
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r = [Signal(intbv(0, mi, ma)) for i in range(delay)]
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@always(clk.posedge, rst.negedge)
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def delayerLogic():
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if rst.val == 0:
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q.next = 0
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for i in range(delay):
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r[i].next = 0
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else:
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r[0].next = d
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q.next = r[delay - 1].val
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for i in range(delay - 1):
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r[i + 1].next = r[i].val
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return delayerLogic
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def opposite(pos, neg):
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""" Take the opposite of a number.
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pos -- in : original number
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neg -- out : opposite number
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"""
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@always_comb
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def oppositeLogic():
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neg.next = -pos.val
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return oppositeLogic
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def adder(op1, op2, res):
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""" Adder.
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op1 -- in : first operand
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op2 -- in : second operand
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res -- out : result of the addition
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"""
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@always_comb
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def addLogic():
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res.next = op1.val + op2.val
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return addLogic
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def register(clk, rst, d, q):
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""" Register.
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clk, rst -- in : clock and negative reset
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d -- in : next value
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q -- out : current value
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"""
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@always(clk.posedge, rst.negedge)
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def registerLogic():
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if rst.val == 0:
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q.next = 0
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else:
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q.next = d.val
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return registerLogic
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def cmp2(op1, op2, res):
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""" 2-input comparator.
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op1 -- in : first operand
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op2 -- in : second operand
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res -- out : compare result (0 if op2 < op1, 1 otherwise)
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"""
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@always_comb
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def cmp2Logic():
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if op1.val > op2.val:
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res.next = 0
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else:
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res.next = 1
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return cmp2Logic
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def mux2(in1, in2, sel, outSel):
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""" 2-input mux.
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in1 -- in : first input signal
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in2 -- in : second input signal
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sel -- in : 1-bit control signal
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outSel -- out : selected output signal
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"""
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@always_comb
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def mux2Logic():
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if sel.val == 0:
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outSel.next = in2.val
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else:
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outSel.next = in1.val
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return mux2Logic
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def orGate(op1, op2, res):
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""" 2-input OR gate.
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op1 -- in : first operand
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op2 -- in : second operand
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res -- out : result
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"""
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@always_comb
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def orGateLogic():
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res.next = op1.val or op2.val
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return orGateLogic
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def min4(op1, op2, op3, op4, res1, res2, res3, q = 8):
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""" Selects the minimum between 4 values.
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q -- width of the signals to compare
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op1 -- in : first input signal
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op2 -- in : second input signal
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op3 -- in : third input signal
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op4 -- in : fourth input signal
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res1 -- out : partial code of the minimum value
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res2 -- out : partial code of the minimum value
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res3 -- out : partial code of the minimum value
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"""
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op5 = Signal(intbv(0, 0, 2**q))
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op6 = Signal(intbv(0, 0, 2**q))
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cmp2_i0 = cmp2(op1, op2, res1)
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cmp2_i1 = cmp2(op3, op4, res2)
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mux2_i0 = mux2(op1, op2, res1, op5)
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mux2_i1 = mux2(op3, op4, res2, op6)
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cmp2_i2 = cmp2(op5, op6, res3)
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return cmp2_i0, cmp2_i1, mux2_i0, mux2_i1, cmp2_i2
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def mux4(in1, in2, in3, in4, sel, outSel):
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""" 4-input mux.
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in1 -- in : first input signal
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in2 -- in : second input signal
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in3 -- in : third input signal
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in4 -- in : fourth input signal
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sel -- in : 2-bit control signal
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outSel -- out : selected output signal
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"""
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@always_comb
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def mux4Logic():
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if sel.val == 0:
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outSel.next = in1.val
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elif sel.val == 1:
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outSel.next = in2.val
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elif sel.val == 2:
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outSel.next = in3.val
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else:
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outSel.next = in4.val
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return mux4Logic
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def cod2(in1, in2, in3, outCod):
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""" 2-bit coder.
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in1 -- in : 1-bit first input signal
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in2 -- in : 1-bit second input signal
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in3 -- in : 1-bit third input signal
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outCod -- out : 2-bit coded value
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"""
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tmp = intbv(0, 0, 8)
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@always_comb
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def cod2Logic():
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tmp = concat(bool(in1.val), bool(in2.val), bool(in3.val))
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if tmp == 5:
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outCod.next = 0
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elif tmp == 7:
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outCod.next = 0
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elif tmp == 1:
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outCod.next = 1
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elif tmp == 3:
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outCod.next = 1
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elif tmp == 2:
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outCod.next = 2
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elif tmp == 6:
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outCod.next = 2
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elif tmp == 0:
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outCod.next = 3
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else:
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outCod.next = 3
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return cod2Logic
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def cod3(inSig, outCod):
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""" 3-bit coder.
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inSig -- in : 7 1-bit input signals
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outCod -- out : 3-bit coded value
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"""
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tmp = intbv(0, 0, 8)
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@instance
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def cod3Logic():
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while 1:
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tmp[0] = ((not inSig[6].val) and (not inSig[5].val) and (not inSig[3].val)) or ((not inSig[6].val) and inSig[5].val and (not inSig[2].val)) or (inSig[6].val and (not inSig[4].val) and (not inSig[1].val)) or ((inSig[6].val) and (inSig[4].val) and (not inSig[0].val));
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tmp[1] = ((not inSig[6].val) and (not inSig[5].val)) or (inSig[6].val and (not inSig[4].val));
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tmp[2] = not inSig[6].val
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outCod.next = tmp
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yield inSig[0], inSig[1], inSig[2], inSig[3], inSig[4], inSig[5], inSig[6]
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return cod3Logic
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def min8(op, res, q = 8):
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""" Selects the minimum between 8 values.
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q -- accumulated distance width
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op -- in : input signals
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res -- out : code of the minimum value
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"""
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tmp = [Signal(intbv(0, 0, 2**q)) for i in range(6)]
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cmp2_i0 = cmp2(op[0], op[1], res[0])
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cmp2_i1 = cmp2(op[2], op[3], res[1])
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cmp2_i2 = cmp2(op[4], op[5], res[2])
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cmp2_i3 = cmp2(op[6], op[7], res[3])
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mux2_i0 = mux2(op[0], op[1], res[0], tmp[0])
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mux2_i1 = mux2(op[2], op[3], res[1], tmp[1])
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mux2_i2 = mux2(op[4], op[5], res[2], tmp[2])
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mux2_i3 = mux2(op[6], op[7], res[3], tmp[3])
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cmp2_i4 = cmp2(tmp[0], tmp[1], res[4])
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cmp2_i5 = cmp2(tmp[2], tmp[3], res[5])
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mux2_i4 = mux2(tmp[0], tmp[1], res[4], tmp[4])
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mux2_i5 = mux2(tmp[2], tmp[3], res[5], tmp[5])
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cmp2_i6 = cmp2(tmp[4], tmp[5], res[6])
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return cmp2_i0, cmp2_i1, cmp2_i2, cmp2_i3, mux2_i0, mux2_i1, mux2_i2, mux2_i3, cmp2_i4, cmp2_i5, mux2_i4, mux2_i5, cmp2_i6
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def mux8(in1, in2, in3, in4, in5, in6, in7, in8, sel, outSel):
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""" 8-input mux (4 bits per input).
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in1 -- in : first input signals
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in2 -- in : second input signals
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in3 -- in : third input signals
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in4 -- in : fourth input signals
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in5 -- in : fifth input signals
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in6 -- in : sixth input signals
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in7 -- in : seventh input signals
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in8 -- in : eighth input signals
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sel -- in : 3-bit control signal
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outSel -- out : selected output signals
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"""
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@instance
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def mux8Logic():
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while 1:
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if sel.val == 0:
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for i in range(4):
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outSel[i].next = in1[i].val
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elif sel.val == 1:
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for i in range(4):
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outSel[i].next = in2[i].val
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elif sel.val == 2:
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for i in range(4):
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outSel[i].next = in3[i].val
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elif sel.val == 3:
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for i in range(4):
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outSel[i].next = in4[i].val
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elif sel.val == 4:
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for i in range(4):
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outSel[i].next = in5[i].val
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elif sel.val == 5:
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for i in range(4):
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outSel[i].next = in6[i].val
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elif sel.val == 6:
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for i in range(4):
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outSel[i].next = in7[i].val
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else:
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for i in range(4):
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outSel[i].next = in8[i].val
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yield in1[0], in1[1], in1[2], in1[3], in2[0], in2[1], in2[2], in2[3], in3[0], in3[1], in3[2], in3[3], in4[0], in4[1], in4[2], in4[3], in5[0], in5[1], in5[2], in5[3], in6[0], in6[1], in6[2], in6[3], in7[0], in7[1], in7[2], in7[3], in8[0], in8[1], in8[2], in8[3], sel
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return mux8Logic
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| 322 |
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def sub(op1, op2, res):
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| 323 |
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""" Substracter.
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| 324 |
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| 325 |
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op1 -- in : first operand
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| 326 |
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op2 -- in : second operand
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| 327 |
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res -- out : result of the substraction
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| 328 |
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"""
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| 330 |
|
|
@instance
|
| 331 |
|
|
def subLogic():
|
| 332 |
|
|
while 1:
|
| 333 |
|
|
if op1.val >= op2.val: # remove that when translate into Verilog (Python expects a positive result)
|
| 334 |
|
|
res.next = op1.val - op2.val
|
| 335 |
|
|
yield op1, op2
|
| 336 |
|
|
return subLogic
|
