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dbrochart |
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---- ----
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---- extInf_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of extInf is
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begin
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process (llr0, llr1, llr2, llr3, zin, a, b)
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variable a_plus_b : std_logic_vector(SIG_WIDTH - 1 downto 0);
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variable a_min_b : std_logic_vector(SIG_WIDTH - 1 downto 0);
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variable tmp : ARRAY7a;
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variable tmp2 : ARRAY4e;
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begin
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a_plus_b := std_logic_vector(conv_signed(((conv_integer(signed(a)) + conv_integer(signed(b))) / 2), SIG_WIDTH));
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a_min_b := std_logic_vector(conv_signed(((conv_integer(signed(a)) - conv_integer(signed(b))) / 2), SIG_WIDTH));
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tmp(0) := conv_integer(unsigned(llr0)) - conv_integer(signed(a_plus_b)) - conv_integer(unsigned(zin(0)));
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tmp(1) := conv_integer(unsigned(llr1)) - conv_integer(signed(a_min_b)) - conv_integer(unsigned(zin(1)));
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tmp(2) := conv_integer(unsigned(llr2)) + conv_integer(signed(a_min_b)) - conv_integer(unsigned(zin(2)));
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tmp(3) := conv_integer(unsigned(llr3)) + conv_integer(signed(a_plus_b)) - conv_integer(unsigned(zin(3)));
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if tmp(0) < tmp(1) then
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tmp(4) := tmp(0);
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else
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tmp(4) := tmp(1);
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end if;
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if tmp(2) < tmp(3) then
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tmp(5) := tmp(2);
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else
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tmp(5) := tmp(3);
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end if;
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if tmp(4) < tmp(5) then
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tmp(6) := tmp(4);
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else
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tmp(6) := tmp(5);
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end if;
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tmp2(0) := tmp(0) - tmp(6);
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tmp2(1) := tmp(1) - tmp(6);
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tmp2(2) := tmp(2) - tmp(6);
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tmp2(3) := tmp(3) - tmp(6);
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if tmp2(0) >= (2 ** Z_WIDTH) then
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zout(0) <= std_logic_vector(conv_unsigned((2 ** Z_WIDTH) - 1, Z_WIDTH));
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else
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zout(0) <= std_logic_vector(conv_unsigned(tmp2(0), Z_WIDTH));
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end if;
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if tmp2(1) >= (2 ** Z_WIDTH) then
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zout(1) <= std_logic_vector(conv_unsigned((2 ** Z_WIDTH) - 1, Z_WIDTH));
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else
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zout(1) <= std_logic_vector(conv_unsigned(tmp2(1), Z_WIDTH));
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end if;
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if tmp2(2) >= (2 ** Z_WIDTH) then
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zout(2) <= std_logic_vector(conv_unsigned((2 ** Z_WIDTH) - 1, Z_WIDTH));
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else
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zout(2) <= std_logic_vector(conv_unsigned(tmp2(2), Z_WIDTH));
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end if;
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if tmp2(3) >= (2 ** Z_WIDTH) then
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zout(3) <= std_logic_vector(conv_unsigned((2 ** Z_WIDTH) - 1, Z_WIDTH));
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else
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zout(3) <= std_logic_vector(conv_unsigned(tmp2(3), Z_WIDTH));
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end if;
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end process;
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end;
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