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[/] [turbocodes/] [trunk/] [src/] [vhdl/] [interleaver_synth.vhd] - Blame information for rev 7

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1 7 dbrochart 
----------------------------------------------------------------------
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----                                                              ----
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----  interleaver_synth.vhd                                       ----
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----                                                              ----
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----  This file is part of the turbo decoder IP core project      ----
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----  http://www.opencores.org/projects/turbocodes/               ----
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----                                                              ----
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----  Author(s):                                                  ----
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----      - David Brochart(dbrochart@opencores.org)               ----
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----                                                              ----
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----  All additional information is available in the README.txt   ----
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----  file.                                                       ----
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----                                                              ----
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2005 Authors                                   ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU Lesser General   ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE. See the GNU Lesser General Public License for more  ----
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---- details.                                                     ----
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----                                                              ----
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---- You should have received a copy of the GNU Lesser General    ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.opencores.org/lgpl.shtml                     ----
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----                                                              ----
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----------------------------------------------------------------------
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architecture synth of interleaver is
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    type ARRAYfrSize is array (0 to FRSIZE - 1) of std_logic_vector(d'length - 1 downto 0);
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    subtype cnt_t is integer range 0 to delay;
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    subtype p_t is integer range 0 to 652;
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    subtype frSize_t is integer range 0 to FRSIZE - 1;
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    subtype frSize2_t is integer range 0 to 2 * FRSIZE - 1;
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    signal array1   : ARRAYfrSize;
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    signal array2   : ARRAYfrSize;
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    signal cnt      : cnt_t;
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    signal i        : frSize_t;
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    signal iTmp     : frSize_t;
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    signal j        : frSize_t;
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    signal full     : std_logic;
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    signal p0       : p_t;
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    signal p1       : p_t;
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    signal p2       : p_t;
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    signal p3       : p_t;
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begin
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    frSize48_g : if FRSIZE = 48 generate
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        p0 <= 11;
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        p1 <= 24;
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        p2 <= 0;
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        p3 <= 24;
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    end generate;
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    frSize64_g : if FRSIZE = 64 generate
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        p0 <= 7;
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        p1 <= 34;
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        p2 <= 32;
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        p3 <= 2;
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    end generate;
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    frSize212_g : if FRSIZE = 212 generate
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        p0 <= 13;
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        p1 <= 106;
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        p2 <= 108;
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        p3 <= 2;
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    end generate;
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    frSize220_g : if FRSIZE = 220 generate
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        p0 <= 23;
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        p1 <= 112;
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        p2 <= 4;
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        p3 <= 116;
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    end generate;
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    frSize228_g : if FRSIZE = 228 generate
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        p0 <= 17;
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        p1 <= 116;
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        p2 <= 72;
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        p3 <= 188;
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    end generate;
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    frSize424_g : if FRSIZE = 424 generate
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        p0 <= 11;
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        p1 <= 6;
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        p2 <= 8;
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        p3 <= 2;
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    end generate;
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    frSize432_g : if FRSIZE = 432 generate
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        p0 <= 13;
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        p1 <= 0;
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        p2 <= 4;
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        p3 <= 8;
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    end generate;
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    frSize440_g : if FRSIZE = 440 generate
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        p0 <= 13;
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        p1 <= 10;
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        p2 <= 4;
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        p3 <= 2;
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    end generate;
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    frSize848_g : if FRSIZE = 848 generate
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        p0 <= 19;
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        p1 <= 2;
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        p2 <= 16;
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        p3 <= 6;
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    end generate;
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    frSize856_g : if FRSIZE = 856 generate
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        p0 <= 19;
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        p1 <= 428;
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        p2 <= 224;
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        p3 <= 652;
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    end generate;
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    frSize864_g : if FRSIZE = 864 generate
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        p0 <= 19;
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        p1 <= 2;
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        p2 <= 16;
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        p3 <= 6;
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    end generate;
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    frSize752_g : if FRSIZE = 752 generate
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        p0 <= 19;
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        p1 <= 376;
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        p2 <= 224;
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        p3 <= 600;
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    end generate;
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    process (clk, rst)
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        variable p      : frSize2_t;
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        variable iTmp1  : frSize2_t;
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        variable iTmp2  : frSize2_t;
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        variable iTmp3  : frSize2_t;
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        variable ii     : frSize_t;
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        variable jj     : frSize_t;
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    begin
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        if rst = '0' then
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            cnt     <= 0;
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            i       <= 0;
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            j       <= 0;
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            iTmp    <= 0;
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            full    <= '0';
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            q       <= std_logic_vector(conv_unsigned(0, q'length));
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            for k in 0 to FRSIZE - 1 loop
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                array1(k) <= (others => '0');
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                array2(k) <= (others => '0');
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            end loop;
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        elsif clk = '1' and clk'event then
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            if cnt < delay then
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                cnt <= cnt + 1;
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            else
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                if j mod 4 = 0 then
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                    p := 0;
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                elsif j mod 4 = 1 then
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                    p := FRSIZE / 2 + p1;
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                elsif j mod 4 = 2 then
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                    p := p2;
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                else    -- if j mod 4 = 3 then
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                    p := FRSIZE / 2 + p3;
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                end if;
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                iTmp1 := iTmp + p0;
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                if iTmp1 >= FRSIZE then
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                    iTmp2 := iTmp1 - FRSIZE;
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                else
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                    iTmp2 := iTmp1;
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                end if;
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                iTmp <= iTmp2;
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                iTmp3 := iTmp2 + p + 1;
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                if iTmp3 >= 2 * FRSIZE then
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                    i <= iTmp3 - 2 * FRSIZE;
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                elsif iTmp3 >= FRSIZE then
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                    i <= iTmp3 - FRSIZE;
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                else
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                    i <= iTmp3;
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                end if;
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                if j = (FRSIZE - 1) then
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                    j       <= 0;
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                    full    <= not full;
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                else
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                    j <= j + 1;
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                end if;
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                if way = 0 then
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                    ii := i;
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                    jj := j;
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                else
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                    ii := j;
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                    jj := i;
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                end if;
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                if full = '0' then
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                    array1(jj) <= d;
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                    q <= array2(ii);
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                else
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                    array2(jj) <= d;
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                    q <= array1(ii);
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                end if;
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            end if;
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        end if;
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    end process;
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end;

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