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dbrochart |
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---- ----
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---- iteration_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of iteration is
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signal zout1 : ARRAY4c;
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signal zout2 : ARRAY4c;
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signal zout1Perm : ARRAY4c;
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signal zoutInt1 : ARRAY4c;
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signal zout2Int : ARRAY4c;
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signal tmp0 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
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signal tmp1 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
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signal tmp2 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
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signal tmp3 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
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signal tmp4 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
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signal tmp5 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
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signal tmp6 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
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signal tmp7 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
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signal tmp8 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
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signal tmp9 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
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signal tmp10 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
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signal tmp11 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
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signal abDel1Perm : ARRAY2a;
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signal abDel1PermInt: ARRAY2a;
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signal aDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal bDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal yDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal wDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal yIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal wIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal aDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal bDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal yDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal wDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal aDecInt : std_logic;
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signal bDecInt : std_logic;
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signal aDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal bDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal yDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal wDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal yIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal wIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal yIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal wIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
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begin
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sova_i0 : sova port map (
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clk => clk,
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rst => rst,
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aNoisy => a,
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bNoisy => b,
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yNoisy => y,
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wNoisy => w,
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zin => zin,
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zout => zout1,
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aClean => aDec,
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bClean => bDec
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);
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zPermut_i0 : zPermut generic map (
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flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
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)
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port map (
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flipflop => flipflop,
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z => zout1,
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zPerm => zout1Perm
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);
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tmp0 <= zout1Perm(0) & zout1Perm(1) & zout1Perm(2) & zout1Perm(3) & abDel1Perm(0) & abDel1Perm(1);
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interleaver_i0 : interleaver generic map (
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delay => TREL1_LEN + TREL2_LEN + 2 + delay,
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way => 0
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)
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port map (
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clk => clk,
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rst => rst,
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d => tmp0,
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q => tmp1
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);
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zoutInt1(0) <= tmp1(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 3 + SIG_WIDTH * 2);
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zoutInt1(1) <= tmp1(Z_WIDTH * 3 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 2 + SIG_WIDTH * 2);
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zoutInt1(2) <= tmp1(Z_WIDTH * 2 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 1 + SIG_WIDTH * 2);
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zoutInt1(3) <= tmp1(Z_WIDTH * 1 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 0 + SIG_WIDTH * 2);
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abDel1PermInt(0) <= tmp1(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
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abDel1PermInt(1) <= tmp1(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
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tmp2 <= a & b & y & w & yInt & wInt;
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delayer_i0 : delayer generic map (
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delay => TREL1_LEN + TREL2_LEN
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)
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port map (
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clk => clk,
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rst => rst,
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d => tmp2,
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q => tmp3
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);
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aDel1 <= tmp3(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
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bDel1 <= tmp3(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
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yDel1 <= tmp3(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
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wDel1 <= tmp3(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
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yIntDel1 <= tmp3(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
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wIntDel1 <= tmp3(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
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abPermut_i0 : abPermut generic map (
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flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
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)
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port map (
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flipflop => flipflop,
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a => aDel1,
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b => bDel1,
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abPerm => abDel1Perm
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);
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tmp4 <= aDel1 & bDel1 & yDel1 & wDel1;
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delayer_i1 : delayer generic map (
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delay => FRSIZE
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)
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port map (
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clk => clk,
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rst => rst,
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d => tmp4,
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q => tmp5
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);
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aDel2 <= tmp5(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
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bDel2 <= tmp5(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
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yDel2 <= tmp5(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
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wDel2 <= tmp5(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
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sova_i1 : sova port map (
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clk => clk,
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rst => rst,
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aNoisy => abDel1PermInt(1),
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bNoisy => abDel1PermInt(0),
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yNoisy => yIntDel1,
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wNoisy => wIntDel1,
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zin => zoutInt1,
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zout => zout2,
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aClean => aDecInt,
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bClean => bDecInt
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);
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tmp6 <= zout2(0) & zout2(1) & zout2(2) & zout2(3);
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deinterleaver_i0 : interleaver generic map (
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delay => 2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay,
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way => 1
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)
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port map (
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clk => clk,
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rst => rst,
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d => tmp6,
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q => tmp7
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);
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zout2Int(0) <= tmp7(Z_WIDTH * 4 - 1 downto Z_WIDTH * 3);
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zout2Int(1) <= tmp7(Z_WIDTH * 3 - 1 downto Z_WIDTH * 2);
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zout2Int(2) <= tmp7(Z_WIDTH * 2 - 1 downto Z_WIDTH * 1);
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zout2Int(3) <= tmp7(Z_WIDTH * 1 - 1 downto Z_WIDTH * 0);
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zPermut_i1 : zPermut generic map (
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flip => (2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay) mod 2
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)
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port map (
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flipflop => flipflop,
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z => zout2Int,
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zPerm => zout
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);
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tmp8 <= aDel2 & bDel2 & yDel2 & wDel2 & yIntDel1 & wIntDel1;
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delayer_i2 : delayer generic map (
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delay => TREL1_LEN + TREL2_LEN
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)
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port map (
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clk => clk,
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rst => rst,
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d => tmp8,
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q => tmp9
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);
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aDel3 <= tmp9(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
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bDel3 <= tmp9(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
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yDel3 <= tmp9(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
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wDel3 <= tmp9(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
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yIntDel3 <= tmp9(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
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wIntDel3 <= tmp9(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
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tmp10 <= aDel3 & bDel3 & yDel3 & wDel3 & yIntDel3 & wIntDel3 & yIntDel4 & wIntDel4;
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delayer_i3 : delayer generic map (
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delay => FRSIZE
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)
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port map (
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clk => clk,
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rst => rst,
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d => tmp10,
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q => tmp11
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);
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aDel <= tmp11(SIG_WIDTH * 8 - 1 downto SIG_WIDTH * 7);
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bDel <= tmp11(SIG_WIDTH * 7 - 1 downto SIG_WIDTH * 6);
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yDel <= tmp11(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
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wDel <= tmp11(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
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yIntDel4 <= tmp11(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
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wIntDel4 <= tmp11(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
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yIntDel <= tmp11(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
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wIntDel <= tmp11(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
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end;
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