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[/] [turbocodes/] [trunk/] [src/] [vhdl/] [punct_synth.vhd] - Blame information for rev 7

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1 7 dbrochart
----------------------------------------------------------------------
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----                                                              ----
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----  punct_synth.vhd                                             ----
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----                                                              ----
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----  This file is part of the turbo decoder IP core project      ----
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----  http://www.opencores.org/projects/turbocodes/               ----
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----                                                              ----
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----  Author(s):                                                  ----
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----      - David Brochart(dbrochart@opencores.org)               ----
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----                                                              ----
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----  All additional information is available in the README.txt   ----
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----  file.                                                       ----
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----                                                              ----
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2005 Authors                                   ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU Lesser General   ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE. See the GNU Lesser General Public License for more  ----
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---- details.                                                     ----
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----                                                              ----
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---- You should have received a copy of the GNU Lesser General    ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.opencores.org/lgpl.shtml                     ----
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----                                                              ----
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----------------------------------------------------------------------
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architecture synth of punct is
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    subtype cnt_t is integer range 0 to 6;
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    signal pattern  : std_logic_vector(0 to 11);
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    signal cntMax   : cnt_t;
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    signal cnt      : cnt_t;
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    signal ySel     : std_logic;
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    signal wSel     : std_logic;
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begin
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    pattern_g13 : if RATE = 13 generate
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        pattern <= "110000000000";
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        cntMax  <= 1;
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    end generate;
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    pattern_g25 : if RATE = 25 generate
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        pattern <= "111000000000";
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        cntMax  <= 2;
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    end generate;
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    pattern_g12 : if RATE = 12 generate
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        pattern <= "100000000000";
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        cntMax  <= 1;
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    end generate;
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    pattern_g23 : if RATE = 23 generate
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        pattern <= "100000000000";
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        cntMax  <= 2;
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    end generate;
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    pattern_g34 : if RATE = 34 generate
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        pattern <= "100000000000";
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        cntMax  <= 3;
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    end generate;
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    pattern_g45 : if RATE = 45 generate
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        pattern <= "100000000000";
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        cntMax  <= 4;
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    end generate;
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    pattern_g67 : if RATE = 67 generate
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        pattern <= "100000000000";
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        cntMax  <= 6;
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    end generate;
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    process(clk, rst)
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    begin
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        if rst = '0' then
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            ySel    <= '0';
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            wSel    <= '0';
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            cnt     <= 0;
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        elsif clk = '1' and clk'event then
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            if cnt < cntMax - 1 then
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                cnt <= cnt + 1;
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            else
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                cnt <= 0;
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            end if;
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            ySel <= pattern(cnt);
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            wSel <= pattern(cntMax + cnt);
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        end if;
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    end process;
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    yPunct      <=  y       when ySel = '1'     else
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                    (others => '0');
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    wPunct      <=  w       when wSel = '1'     else
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                    (others => '0');
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    yIntPunct   <=  yInt    when ySel = '1'     else
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                    (others => '0');
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    wIntPunct   <=  wInt    when wSel = '1'     else
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                    (others => '0');
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end;

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