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[/] [turbocodes/] [trunk/] [src/] [vhdl/] [reg_e.vhd] - Blame information for rev 7

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1 7 dbrochart
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----                                                              ----
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----  reg_e.vhd                                                   ----
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----                                                              ----
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----  This file is part of the turbo decoder IP core project      ----
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----  http://www.opencores.org/projects/turbocodes/               ----
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----                                                              ----
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----  Author(s):                                                  ----
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----      - David Brochart(dbrochart@opencores.org)               ----
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----                                                              ----
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----  All additional information is available in the README.txt   ----
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----  file.                                                       ----
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----                                                              ----
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2005 Authors                                   ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU Lesser General   ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE. See the GNU Lesser General Public License for more  ----
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---- details.                                                     ----
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----                                                              ----
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---- You should have received a copy of the GNU Lesser General    ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.opencores.org/lgpl.shtml                     ----
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----                                                              ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity reg is   -- register
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    port    (
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            clk     : in  std_logic;        -- clock
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            rst     : in  std_logic;        -- negative reset
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            d       : in  std_logic_vector; -- next value
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            q       : out std_logic_vector  -- current value
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            );
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end reg;

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