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dbrochart |
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---- ----
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---- trellis2_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of trellis2 is
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signal revWeight : ARRAY_4xTREL2_LEN;
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signal pathIdReg : ARRAY8d;
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signal reg : ARRAY_TREL2_LENx8;
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begin
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process (clk, rst)
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variable free : std_logic_vector(7 downto 0);
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variable freeBeg : std_logic_vector(7 downto 0);
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variable pastState : ARRAY8d;
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variable pathId : ARRAY8d;
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variable freePathId : INT3BIT;
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variable op : ARRAY4a;
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variable tmp : ARRAY4a;
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variable revWeightTmp : ARRAY_4xTREL2_LEN;
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variable revWeightFilt : ARRAY3a;
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variable notZero : ARRAY6b;
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variable minTmp : std_logic_vector(0 to 2);
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variable ind : ARRAY6b;
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variable tmp4 : std_logic_vector(ACC_DIST_WIDTH downto 0);
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begin
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if rst = '0' then
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for i in 0 to 3 loop
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for j in 0 to TREL2_LEN - 1 loop
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revWeight(i * TREL2_LEN + j) <= (others => '0');
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end loop;
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end loop;
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a <= '0';
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b <= '0';
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llr0 <= (others => '0');
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llr1 <= (others => '0');
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llr2 <= (others => '0');
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llr3 <= (others => '0');
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for i in 0 to 7 loop
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pathIdReg(i) <= i;
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for j in 0 to TREL2_LEN - 1 loop
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reg(j * 8 + i) <= "00";
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end loop;
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end loop;
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elsif clk = '1' and clk'event then
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free := "11111111";
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for i in 0 to 7 loop
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pastState(i) := TRANS2STATE(i * 4 + conv_integer(unsigned(selTrans(i))));
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pathId(i) := pathIdReg(pastState(i));
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free(pathId(i)) := '0';
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end loop;
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freeBeg := "11111111";
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for i in 0 to 7 loop
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if freeBeg(pathId(i)) = '1' then
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reg(0 * 8 + pathId(i)) <= selTrans(i);
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freeBeg(pathId(i)) := '0';
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pathIdReg(i) <= pathId(i);
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for j in 0 to TREL2_LEN - 2 loop
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reg((j + 1) * 8 + pathId(i)) <= reg(j * 8 + pathId(i));
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end loop;
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else
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if free(0) = '1' then
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freePathId := 0;
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end if;
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if free(1 downto 0) = "10" then
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freePathId := 1;
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end if;
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if free(2 downto 0) = "100" then
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freePathId := 2;
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end if;
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if free(3 downto 0) = "1000" then
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freePathId := 3;
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end if;
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if free(4 downto 0) = "10000" then
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freePathId := 4;
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end if;
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if free(5 downto 0) = "100000" then
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freePathId := 5;
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end if;
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if free(6 downto 0) = "1000000" then
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freePathId := 6;
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end if;
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if free(7 downto 0) = "10000000" then
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freePathId := 7;
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end if;
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reg(0 * 8 + freePathId) <= selTrans(i);
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free(freePathId) := '0';
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pathIdReg(i) <= freePathId;
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for j in 0 to TREL2_LEN - 2 loop
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reg((j + 1) * 8 + freePathId) <= reg(j * 8 + pathId(i));
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end loop;
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end if;
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end loop;
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a <= reg((TREL2_LEN - 1) * 8 + pathId(conv_integer(unsigned(selState))))(1);
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b <= reg((TREL2_LEN - 1) * 8 + pathId(conv_integer(unsigned(selState))))(0);
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for i in 0 to 3 loop
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for j in 0 to TREL2_LEN - 2 loop
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for k in 0 to 3 loop
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if reg(j * 8 + pathId(conv_integer(unsigned(state(k))))) = std_logic_vector(conv_unsigned(i, 2)) and state(k) /= selState then
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op(k) := weight(k);
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else
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op(k) := std_logic_vector(conv_unsigned((2 ** ACC_DIST_WIDTH) - 1, ACC_DIST_WIDTH));
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end if;
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end loop;
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if conv_integer(unsigned(op(0))) < conv_integer(unsigned(op(1))) then
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tmp(0) := op(0);
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else
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tmp(0) := op(1);
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end if;
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if conv_integer(unsigned(op(2))) < conv_integer(unsigned(op(3))) then
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tmp(1) := op(2);
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else
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tmp(1) := op(3);
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end if;
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if conv_integer(unsigned(tmp(0))) < conv_integer(unsigned(tmp(1))) then
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tmp(2) := tmp(0);
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else
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tmp(2) := tmp(1);
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end if;
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if conv_integer(unsigned(tmp(2))) < conv_integer(unsigned(revWeight(i * TREL2_LEN + j))) then
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revWeightTmp(i * TREL2_LEN + j + 1) := tmp(2);
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else
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revWeightTmp(i * TREL2_LEN + j + 1) := revWeight(i * TREL2_LEN + j);
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end if;
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end loop;
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revWeightTmp(i * TREL2_LEN + 0) := weight(i);
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end loop;
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for j in 0 to 1 loop
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if revWeightTmp(0 * TREL2_LEN + j) = std_logic_vector(conv_unsigned(0, ACC_DIST_WIDTH)) then
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notZero(j * 3 + 0) := 1;
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notZero(j * 3 + 1) := 2;
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notZero(j * 3 + 2) := 3;
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elsif revWeightTmp(1 * TREL2_LEN + j) = std_logic_vector(conv_unsigned(0, ACC_DIST_WIDTH)) then
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notZero(j * 3 + 0) := 0;
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notZero(j * 3 + 1) := 2;
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notZero(j * 3 + 2) := 3;
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elsif revWeightTmp(2 * TREL2_LEN + j) = std_logic_vector(conv_unsigned(0, ACC_DIST_WIDTH)) then
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notZero(j * 3 + 0) := 0;
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notZero(j * 3 + 1) := 1;
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notZero(j * 3 + 2) := 3;
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elsif revWeightTmp(3 * TREL2_LEN + j) = std_logic_vector(conv_unsigned(0, ACC_DIST_WIDTH)) then
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notZero(j * 3 + 0) := 0;
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notZero(j * 3 + 1) := 1;
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notZero(j * 3 + 2) := 2;
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end if;
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if conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 0) * TREL2_LEN + j))) <= conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 1) * TREL2_LEN + j))) then
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minTmp(0) := '0';
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else
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minTmp(0) := '1';
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end if;
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if conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 0) * TREL2_LEN + j))) <= conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 2) * TREL2_LEN + j))) then
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minTmp(1) := '0';
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else
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minTmp(1) := '1';
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end if;
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if conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 1) * TREL2_LEN + j))) <= conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 2) * TREL2_LEN + j))) then
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minTmp(2) := '0';
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else
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minTmp(2) := '1';
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end if;
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if minTmp = "000" then
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ind(j * 3 + 0) := 0;
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ind(j * 3 + 1) := 1;
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ind(j * 3 + 2) := 2;
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elsif minTmp = "001" then
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ind(j * 3 + 0) := 0;
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ind(j * 3 + 1) := 2;
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ind(j * 3 + 2) := 1;
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elsif minTmp = "100" then
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ind(j * 3 + 0) := 1;
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ind(j * 3 + 1) := 0;
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ind(j * 3 + 2) := 2;
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elsif minTmp = "011" then
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ind(j * 3 + 0) := 1;
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ind(j * 3 + 1) := 2;
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ind(j * 3 + 2) := 0;
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elsif minTmp = "110" then
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ind(j * 3 + 0) := 2;
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ind(j * 3 + 1) := 0;
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ind(j * 3 + 2) := 1;
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else -- if minTmp = "111" then
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ind(j * 3 + 0) := 2;
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ind(j * 3 + 1) := 1;
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ind(j * 3 + 2) := 0;
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end if;
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end loop;
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for i in 0 to 2 loop
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tmp(3) := revWeightTmp(notZero(0 * 3 + ind(0 * 3 + i)) * TREL2_LEN + 0);
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tmp4 := std_logic_vector(conv_unsigned(conv_integer(unsigned(revWeightTmp(notZero(1 * 3 + ind(1 * 3 + i)) * TREL2_LEN + 1))) + (2 ** (ACC_DIST_WIDTH - 4)), ACC_DIST_WIDTH + 1));
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if conv_integer(unsigned(tmp(3))) < conv_integer(unsigned(tmp4)) then
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revWeightFilt(ind(0 * 3 + i)) := tmp(3);
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else
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revWeightFilt(ind(0 * 3 + i)) := tmp4(ACC_DIST_WIDTH - 1 downto 0);
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end if;
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end loop;
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for i in 0 to 2 loop
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revWeightTmp(notZero(0 * 3 + i) * TREL2_LEN + 0) := revWeightFilt(i);
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end loop;
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for i in 0 to 3 loop
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for j in 0 to TREL2_LEN - 1 loop
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revWeight(TREL2_LEN * i + j) <= revWeightTmp(TREL2_LEN * i + j);
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end loop;
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end loop;
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llr0 <= revWeight(1 * TREL2_LEN - 1);
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llr1 <= revWeight(2 * TREL2_LEN - 1);
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llr2 <= revWeight(3 * TREL2_LEN - 1);
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llr3 <= revWeight(4 * TREL2_LEN - 1);
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end if;
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end process;
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end;
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