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[/] [tv80/] [trunk/] [rtl/] [app_localcfg/] [lcfg_cfgo_driver.v] - Blame information for rev 105

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1 101 ghutchis 
/* Copyright (c) 2011, Guy Hutchison
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   All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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    * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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    * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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    * Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module lcfg_cfgo_driver
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  (/*AUTOARG*/
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  // Outputs
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  cd_rdata, cfgo_wait_n, cfgo_irdy, cfgo_addr, cfgo_write,
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  cfgo_wr_data,
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  // Inputs
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  clk, reset_n, addr, cd_wdata, mreq_n, rd_n, wr_n, iorq_n, cfgo_trdy,
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  cfgo_rd_data
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  );
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  parameter io_base_addr = 0;
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  input          clk;
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  input          reset_n;
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  // TV80 processor interface
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  input [15:0]   addr;
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  output [7:0]   cd_rdata;
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  input [7:0]    cd_wdata;
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  input          mreq_n;
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  input          rd_n, wr_n;
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  input          iorq_n;
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  output         cfgo_wait_n;
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  // outgoing config interface to system
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  // configuration bus
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  output         cfgo_irdy;
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  input          cfgo_trdy;
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  output [15:0]  cfgo_addr;
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  output         cfgo_write;
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  output [31:0]  cfgo_wr_data;
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  input [31:0]   cfgo_rd_data;
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  wire           rf_irdy;
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  wire           rf_write;
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  /*AUTOWIRE*/
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  // Beginning of automatic wires (for undeclared instantiated-module outputs)
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  wire [7:0]            cfg_addr0;              // From cfgo_regs of lcfg_cfgo_regs.v
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  wire [7:0]            cfg_addr1;              // From cfgo_regs of lcfg_cfgo_regs.v
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  wire [7:0]            cfg_data0_wr_data;      // From cfgo_regs of lcfg_cfgo_regs.v
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  wire [7:0]            cfg_data1_wr_data;      // From cfgo_regs of lcfg_cfgo_regs.v
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  wire [7:0]            cfg_data2_wr_data;      // From cfgo_regs of lcfg_cfgo_regs.v
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  wire [7:0]            cfg_data3_wr_data;      // From cfgo_regs of lcfg_cfgo_regs.v
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  wire [3:0]            rd_stb;                 // From cfgo_regs of lcfg_cfgo_regs.v, ...
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  wire [3:0]            wr_stb;                 // From cfgo_regs of lcfg_cfgo_regs.v, ...
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  // End of automatics
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  parameter s_idle = 0, s_write = 1, s_read = 2, s_ack = 3;
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  reg [31:0]     chold, nxt_chold;
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  reg [3:0]      state, nxt_state;
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  assign rf_irdy = !mreq_n & !iorq_n & ((addr[7:0] & 8'hF8) == io_base_addr);
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  assign rf_write = ~wr_n;
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  assign cfgo_addr = { cfg_addr1, cfg_addr0 };
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  assign cfgo_wr_data = chold;
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  assign cfgo_irdy = state[s_write] | state[s_read];
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  assign cfgo_write = state[s_write];
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  always @*
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    begin
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      nxt_chold = chold;
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      nxt_state = state;
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      case (1'b1) /* verilator lint_off CASEINCOMPLETE */
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        state[s_idle] :
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          begin
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            case (wr_stb)
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              4'b0001 : nxt_chold[7:0] = cfg_data0_wr_data;
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              4'b0010 : nxt_chold[15:8] = cfg_data1_wr_data;
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              4'b0100 : nxt_chold[23:16] = cfg_data2_wr_data;
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              4'b1000 : nxt_chold[31:24] = cfg_data3_wr_data;
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            endcase // case (wr_stb)
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            if (rd_stb[0])
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              nxt_state = 1 << s_read;
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            else if (wr_stb[3])
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              nxt_state = 1 << s_write;
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          end // case: state[s_idle]
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        state[s_write] :
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          begin
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            if (cfgo_trdy)
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              nxt_state = 1 << s_idle;
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          end
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        state[s_read] :
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          begin
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            if (cfgo_trdy)
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              begin
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                nxt_state = 1 << s_ack;
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                nxt_chold = cfgo_rd_data;
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              end
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          end
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        state[s_ack] :
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          begin
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            nxt_state = 1 << s_idle;
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          end
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      endcase // verilator lint_on CASEINCOMPLETE
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    end // always @ *
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  always @(posedge clk or negedge reset_n)
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    begin
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      if (~reset_n)
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        begin
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          state <= 1 << s_idle;
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          chold <= 0;
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        end
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      else
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        begin
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          state <= nxt_state;
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          chold <= nxt_chold;
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        end
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    end
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/* lcfg_cfgo_regs AUTO_TEMPLATE
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 (
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     .rf_trdy                           (cfgo_wait_n),
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     .rf_rd_data                        (cd_rdata[]),
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     .rf_addr                           (addr[]),
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     .rf_wr_data                        (cd_wdata[]),
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     .cfg_data\([0-3]\)_rd_data         (chold[@"(+ (* 8 @) 7)":@"(* 8 @)"]),
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     .cfg_data0_rd_data (chold[7:0]),
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     .cfg_data1_rd_data (chold[15:8]),
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     .cfg_data2_rd_data (chold[23:16]),
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     .cfg_data3_rd_data (chold[31:24]),
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     .cfg_data0_rd_ack                  (state[s_ack]),
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     .cfg_status                        ({4'h0, state}),
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     .cfg_data[1-3]_rd_ack              (1'b1),
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     .cfg_data[0-3]_wr_ack              (state[s_idle]),
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     .cfg_data\([0-3]\)_wr_stb          (wr_stb[\1]),
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     .cfg_data\([0-3]\)_rd_stb          (rd_stb[\1]),
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     .cfg_status ({4'h0,state}),
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 );
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 */
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  lcfg_cfgo_regs cfgo_regs
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    (/*AUTOINST*/
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     // Outputs
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     .rf_trdy                           (cfgo_wait_n),           // Templated
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     .rf_rd_data                        (cd_rdata[7:0]),         // Templated
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     .cfg_addr0                         (cfg_addr0[7:0]),
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     .cfg_addr1                         (cfg_addr1[7:0]),
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     .cfg_data0_wr_stb                  (wr_stb[0]),             // Templated
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     .cfg_data0_rd_stb                  (rd_stb[0]),             // Templated
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     .cfg_data0_wr_data                 (cfg_data0_wr_data[7:0]),
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     .cfg_data1_wr_stb                  (wr_stb[1]),             // Templated
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     .cfg_data1_rd_stb                  (rd_stb[1]),             // Templated
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     .cfg_data1_wr_data                 (cfg_data1_wr_data[7:0]),
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     .cfg_data2_wr_stb                  (wr_stb[2]),             // Templated
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     .cfg_data2_rd_stb                  (rd_stb[2]),             // Templated
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     .cfg_data2_wr_data                 (cfg_data2_wr_data[7:0]),
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     .cfg_data3_wr_stb                  (wr_stb[3]),             // Templated
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     .cfg_data3_rd_stb                  (rd_stb[3]),             // Templated
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     .cfg_data3_wr_data                 (cfg_data3_wr_data[7:0]),
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     // Inputs
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     .clk                               (clk),
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     .reset_n                           (reset_n),
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     .rf_irdy                           (rf_irdy),
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     .rf_write                          (rf_write),
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     .rf_addr                           (addr[3:0]),             // Templated
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     .rf_wr_data                        (cd_wdata[7:0]),         // Templated
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     .cfg_data0_rd_data                 (chold[7:0]),            // Templated
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     .cfg_data0_rd_ack                  (state[s_ack]),          // Templated
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     .cfg_data0_wr_ack                  (state[s_idle]),         // Templated
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     .cfg_data1_rd_data                 (chold[15:8]),           // Templated
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     .cfg_data1_rd_ack                  (1'b1),                  // Templated
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     .cfg_data1_wr_ack                  (state[s_idle]),         // Templated
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     .cfg_data2_rd_data                 (chold[23:16]),          // Templated
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     .cfg_data2_rd_ack                  (1'b1),                  // Templated
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     .cfg_data2_wr_ack                  (state[s_idle]),         // Templated
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     .cfg_data3_rd_data                 (chold[31:24]),          // Templated
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     .cfg_data3_rd_ack                  (1'b1),                  // Templated
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     .cfg_data3_wr_ack                  (state[s_idle]),         // Templated
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     .cfg_status                        ({4'h0, state}));         // Templated
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endmodule

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