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[/] [tv80/] [trunk/] [rtl/] [app_localcfg/] [lcfg_cfgo_regs.v] - Blame information for rev 101

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module lcfg_cfgo_regs (
clk,reset_n,rf_irdy,rf_trdy,rf_write,rf_addr,rf_wr_data,rf_rd_data,cfg_addr0,cfg_addr1,cfg_data0_wr_stb,cfg_data0_rd_stb,cfg_data0_wr_data,cfg_data0_rd_data,cfg_data0_rd_ack,cfg_data0_wr_ack,cfg_data1_wr_stb,cfg_data1_rd_stb,cfg_data1_wr_data,cfg_data1_rd_data,cfg_data1_rd_ack,cfg_data1_wr_ack,cfg_data2_wr_stb,cfg_data2_rd_stb,cfg_data2_wr_data,cfg_data2_rd_data,cfg_data2_rd_ack,cfg_data2_wr_ack,cfg_data3_wr_stb,cfg_data3_rd_stb,cfg_data3_wr_data,cfg_data3_rd_data,cfg_data3_rd_ack,cfg_data3_wr_ack,cfg_status);
input clk;
input reset_n;
input rf_irdy;
output rf_trdy;
input rf_write;
input [3:0] rf_addr;
input [7:0] rf_wr_data;
output [7:0] rf_rd_data;
output [7:0] cfg_addr0;
output [7:0] cfg_addr1;
output cfg_data0_wr_stb;
output cfg_data0_rd_stb;
output [7:0] cfg_data0_wr_data;
input [7:0] cfg_data0_rd_data;
input cfg_data0_rd_ack;
input cfg_data0_wr_ack;
output cfg_data1_wr_stb;
output cfg_data1_rd_stb;
output [7:0] cfg_data1_wr_data;
input [7:0] cfg_data1_rd_data;
input cfg_data1_rd_ack;
input cfg_data1_wr_ack;
output cfg_data2_wr_stb;
output cfg_data2_rd_stb;
output [7:0] cfg_data2_wr_data;
input [7:0] cfg_data2_rd_data;
input cfg_data2_rd_ack;
input cfg_data2_wr_ack;
output cfg_data3_wr_stb;
output cfg_data3_rd_stb;
output [7:0] cfg_data3_wr_data;
input [7:0] cfg_data3_rd_data;
input cfg_data3_rd_ack;
input cfg_data3_wr_ack;
input [7:0] cfg_status;
reg [7:0] rf_rd_data;
reg nxt_rf_trdy;
reg rf_trdy;
reg [7:0] cfg_addr0;
reg [7:0] nxt_cfg_addr0;
reg cfg_addr0_rd_sel;
reg cfg_addr0_wr_sel;
reg [7:0] cfg_addr1;
reg [7:0] nxt_cfg_addr1;
reg cfg_addr1_rd_sel;
reg cfg_addr1_wr_sel;
reg cfg_data0_rd_sel;
reg cfg_data0_wr_sel;
reg cfg_data0_rd_stb;
reg cfg_data0_wr_stb;
reg cfg_data0_wait_n;
reg [7:0] cfg_data0;
reg [7:0] cfg_data0_wr_data;
reg [1:0] sm_cfg_data0_state;
reg [1:0] nxt_sm_cfg_data0_state;
reg cfg_data1_rd_sel;
reg cfg_data1_wr_sel;
reg cfg_data1_rd_stb;
reg cfg_data1_wr_stb;
reg cfg_data1_wait_n;
reg [7:0] cfg_data1;
reg [7:0] cfg_data1_wr_data;
reg [1:0] sm_cfg_data1_state;
reg [1:0] nxt_sm_cfg_data1_state;
reg cfg_data2_rd_sel;
reg cfg_data2_wr_sel;
reg cfg_data2_rd_stb;
reg cfg_data2_wr_stb;
reg cfg_data2_wait_n;
reg [7:0] cfg_data2;
reg [7:0] cfg_data2_wr_data;
reg [1:0] sm_cfg_data2_state;
reg [1:0] nxt_sm_cfg_data2_state;
reg cfg_data3_rd_sel;
reg cfg_data3_wr_sel;
reg cfg_data3_rd_stb;
reg cfg_data3_wr_stb;
reg cfg_data3_wait_n;
reg [7:0] cfg_data3;
reg [7:0] cfg_data3_wr_data;
reg [1:0] sm_cfg_data3_state;
reg [1:0] nxt_sm_cfg_data3_state;
reg cfg_status_rd_sel;
always @*
  begin
    cfg_addr0_rd_sel = (rf_addr[3:0] == 0) & rf_irdy & !rf_write;
    cfg_addr0_wr_sel = (rf_addr[3:0] == 0) & rf_irdy & rf_write;
 
    cfg_addr1_rd_sel = (rf_addr[3:0] == 1) & rf_irdy & !rf_write;
    cfg_addr1_wr_sel = (rf_addr[3:0] == 1) & rf_irdy & rf_write;
 
    cfg_data0_rd_sel = (rf_addr[3:0] == 2) & rf_irdy & !rf_write;
    cfg_data0_wr_sel = (rf_addr[3:0] == 2) & rf_irdy & rf_write;
 
    cfg_data1_rd_sel = (rf_addr[3:0] == 3) & rf_irdy & !rf_write;
    cfg_data1_wr_sel = (rf_addr[3:0] == 3) & rf_irdy & rf_write;
 
    cfg_data2_rd_sel = (rf_addr[3:0] == 4) & rf_irdy & !rf_write;
    cfg_data2_wr_sel = (rf_addr[3:0] == 4) & rf_irdy & rf_write;
 
    cfg_data3_rd_sel = (rf_addr[3:0] == 5) & rf_irdy & !rf_write;
    cfg_data3_wr_sel = (rf_addr[3:0] == 5) & rf_irdy & rf_write;
 
    cfg_status_rd_sel = (rf_addr[3:0] == 6) & rf_irdy & !rf_write;
  end
always @*
  begin
    case (1'b1)
      cfg_addr0_rd_sel : rf_rd_data = cfg_addr0;
      cfg_addr1_rd_sel : rf_rd_data = cfg_addr1;
      cfg_data0_rd_sel : rf_rd_data = cfg_data0;
      cfg_data1_rd_sel : rf_rd_data = cfg_data1;
      cfg_data2_rd_sel : rf_rd_data = cfg_data2;
      cfg_data3_rd_sel : rf_rd_data = cfg_data3;
      cfg_status_rd_sel : rf_rd_data = cfg_status;
      default : rf_rd_data = 8'b0;
    endcase
  end
always @*
  begin
    if (rf_trdy) nxt_rf_trdy = 0;
    else if (rf_irdy) nxt_rf_trdy = cfg_data0_wait_n & cfg_data1_wait_n & cfg_data2_wait_n & cfg_data3_wait_n;
    else nxt_rf_trdy = 0;
  end
always @(posedge clk or negedge reset_n)
  begin
    if (~reset_n) rf_trdy <= #1 0;
    else rf_trdy <= #1 nxt_rf_trdy;
  end
// config: cfg_addr0
always @*
  begin
    if (cfg_addr0_wr_sel) nxt_cfg_addr0 = rf_wr_data;
    else nxt_cfg_addr0 = cfg_addr0;
  end
always @(posedge clk or negedge reset_n)
  begin
    if (~reset_n) cfg_addr0 <= #1 8'h0;
    else cfg_addr0 <= #1 nxt_cfg_addr0;
  end
// config: cfg_addr1
always @*
  begin
    if (cfg_addr1_wr_sel) nxt_cfg_addr1 = rf_wr_data;
    else nxt_cfg_addr1 = cfg_addr1;
  end
always @(posedge clk or negedge reset_n)
  begin
    if (~reset_n) cfg_addr1 <= #1 8'h0;
    else cfg_addr1 <= #1 nxt_cfg_addr1;
  end
// state machine sm_cfg_data0
parameter st_sm_cfg_data0_w_clear = 0;
parameter st_sm_cfg_data0_idle = 1;
parameter st_sm_cfg_data0_wr_req = 2;
parameter st_sm_cfg_data0_rd_req = 3;
always @*
  begin
    cfg_data0_rd_stb = 0;
    cfg_data0_wr_stb = 0;
    cfg_data0_wait_n = 1;
    nxt_sm_cfg_data0_state = sm_cfg_data0_state;
    case (sm_cfg_data0_state)
    st_sm_cfg_data0_w_clear :
      begin
        if (~(cfg_data0_rd_sel | cfg_data0_wr_sel))
        begin
        nxt_sm_cfg_data0_state = st_sm_cfg_data0_idle;
        end
      end
    st_sm_cfg_data0_idle :
      begin
        if (cfg_data0_rd_sel)
        begin
        nxt_sm_cfg_data0_state = st_sm_cfg_data0_rd_req;
        cfg_data0_wait_n = 0;
        end
        else if (cfg_data0_wr_sel)
        begin
        nxt_sm_cfg_data0_state = st_sm_cfg_data0_wr_req;
        cfg_data0_wait_n = 0;
        end
      end
    st_sm_cfg_data0_wr_req :
      begin
        if (cfg_data0_wr_ack)
        begin
        nxt_sm_cfg_data0_state = st_sm_cfg_data0_w_clear;
        end
        else if (!cfg_data0_wr_ack)
        begin
        cfg_data0_wait_n = 0;
        end
        cfg_data0_wr_stb = 1;
      end
    st_sm_cfg_data0_rd_req :
      begin
        if (cfg_data0_rd_ack)
        begin
        nxt_sm_cfg_data0_state = st_sm_cfg_data0_w_clear;
        end
        else if (!cfg_data0_rd_ack)
        begin
        cfg_data0_wait_n = 0;
        end
        cfg_data0_rd_stb = 1;
      end
    endcase
  end
always @(posedge clk or negedge reset_n)
  begin
    if(~reset_n)
    sm_cfg_data0_state <= #1 st_sm_cfg_data0_idle;
    else
    sm_cfg_data0_state <= #1 nxt_sm_cfg_data0_state;
  end
always @*
  begin
    cfg_data0_wr_data = rf_wr_data;
    cfg_data0 = cfg_data0_rd_data;
  end
// state machine sm_cfg_data1
parameter st_sm_cfg_data1_w_clear = 0;
parameter st_sm_cfg_data1_idle = 1;
parameter st_sm_cfg_data1_wr_req = 2;
parameter st_sm_cfg_data1_rd_req = 3;
always @*
  begin
    cfg_data1_rd_stb = 0;
    cfg_data1_wr_stb = 0;
    cfg_data1_wait_n = 1;
    nxt_sm_cfg_data1_state = sm_cfg_data1_state;
    case (sm_cfg_data1_state)
    st_sm_cfg_data1_w_clear :
      begin
        if (~(cfg_data1_rd_sel | cfg_data1_wr_sel))
        begin
        nxt_sm_cfg_data1_state = st_sm_cfg_data1_idle;
        end
      end
    st_sm_cfg_data1_idle :
      begin
        if (cfg_data1_rd_sel)
        begin
        nxt_sm_cfg_data1_state = st_sm_cfg_data1_rd_req;
        cfg_data1_wait_n = 0;
        end
        else if (cfg_data1_wr_sel)
        begin
        nxt_sm_cfg_data1_state = st_sm_cfg_data1_wr_req;
        cfg_data1_wait_n = 0;
        end
      end
    st_sm_cfg_data1_wr_req :
      begin
        if (cfg_data1_wr_ack)
        begin
        nxt_sm_cfg_data1_state = st_sm_cfg_data1_w_clear;
        end
        else if (!cfg_data1_wr_ack)
        begin
        cfg_data1_wait_n = 0;
        end
        cfg_data1_wr_stb = 1;
      end
    st_sm_cfg_data1_rd_req :
      begin
        if (cfg_data1_rd_ack)
        begin
        nxt_sm_cfg_data1_state = st_sm_cfg_data1_w_clear;
        end
        else if (!cfg_data1_rd_ack)
        begin
        cfg_data1_wait_n = 0;
        end
        cfg_data1_rd_stb = 1;
      end
    endcase
  end
always @(posedge clk or negedge reset_n)
  begin
    if(~reset_n)
    sm_cfg_data1_state <= #1 st_sm_cfg_data1_idle;
    else
    sm_cfg_data1_state <= #1 nxt_sm_cfg_data1_state;
  end
always @*
  begin
    cfg_data1_wr_data = rf_wr_data;
    cfg_data1 = cfg_data1_rd_data;
  end
// state machine sm_cfg_data2
parameter st_sm_cfg_data2_w_clear = 0;
parameter st_sm_cfg_data2_idle = 1;
parameter st_sm_cfg_data2_wr_req = 2;
parameter st_sm_cfg_data2_rd_req = 3;
always @*
  begin
    cfg_data2_rd_stb = 0;
    cfg_data2_wr_stb = 0;
    cfg_data2_wait_n = 1;
    nxt_sm_cfg_data2_state = sm_cfg_data2_state;
    case (sm_cfg_data2_state)
    st_sm_cfg_data2_w_clear :
      begin
        if (~(cfg_data2_rd_sel | cfg_data2_wr_sel))
        begin
        nxt_sm_cfg_data2_state = st_sm_cfg_data2_idle;
        end
      end
    st_sm_cfg_data2_idle :
      begin
        if (cfg_data2_rd_sel)
        begin
        nxt_sm_cfg_data2_state = st_sm_cfg_data2_rd_req;
        cfg_data2_wait_n = 0;
        end
        else if (cfg_data2_wr_sel)
        begin
        nxt_sm_cfg_data2_state = st_sm_cfg_data2_wr_req;
        cfg_data2_wait_n = 0;
        end
      end
    st_sm_cfg_data2_wr_req :
      begin
        if (cfg_data2_wr_ack)
        begin
        nxt_sm_cfg_data2_state = st_sm_cfg_data2_w_clear;
        end
        else if (!cfg_data2_wr_ack)
        begin
        cfg_data2_wait_n = 0;
        end
        cfg_data2_wr_stb = 1;
      end
    st_sm_cfg_data2_rd_req :
      begin
        if (cfg_data2_rd_ack)
        begin
        nxt_sm_cfg_data2_state = st_sm_cfg_data2_w_clear;
        end
        else if (!cfg_data2_rd_ack)
        begin
        cfg_data2_wait_n = 0;
        end
        cfg_data2_rd_stb = 1;
      end
    endcase
  end
always @(posedge clk or negedge reset_n)
  begin
    if(~reset_n)
    sm_cfg_data2_state <= #1 st_sm_cfg_data2_idle;
    else
    sm_cfg_data2_state <= #1 nxt_sm_cfg_data2_state;
  end
always @*
  begin
    cfg_data2_wr_data = rf_wr_data;
    cfg_data2 = cfg_data2_rd_data;
  end
// state machine sm_cfg_data3
parameter st_sm_cfg_data3_w_clear = 0;
parameter st_sm_cfg_data3_idle = 1;
parameter st_sm_cfg_data3_wr_req = 2;
parameter st_sm_cfg_data3_rd_req = 3;
always @*
  begin
    cfg_data3_rd_stb = 0;
    cfg_data3_wr_stb = 0;
    cfg_data3_wait_n = 1;
    nxt_sm_cfg_data3_state = sm_cfg_data3_state;
    case (sm_cfg_data3_state)
    st_sm_cfg_data3_w_clear :
      begin
        if (~(cfg_data3_rd_sel | cfg_data3_wr_sel))
        begin
        nxt_sm_cfg_data3_state = st_sm_cfg_data3_idle;
        end
      end
    st_sm_cfg_data3_idle :
      begin
        if (cfg_data3_rd_sel)
        begin
        nxt_sm_cfg_data3_state = st_sm_cfg_data3_rd_req;
        cfg_data3_wait_n = 0;
        end
        else if (cfg_data3_wr_sel)
        begin
        nxt_sm_cfg_data3_state = st_sm_cfg_data3_wr_req;
        cfg_data3_wait_n = 0;
        end
      end
    st_sm_cfg_data3_wr_req :
      begin
        if (cfg_data3_wr_ack)
        begin
        nxt_sm_cfg_data3_state = st_sm_cfg_data3_w_clear;
        end
        else if (!cfg_data3_wr_ack)
        begin
        cfg_data3_wait_n = 0;
        end
        cfg_data3_wr_stb = 1;
      end
    st_sm_cfg_data3_rd_req :
      begin
        if (cfg_data3_rd_ack)
        begin
        nxt_sm_cfg_data3_state = st_sm_cfg_data3_w_clear;
        end
        else if (!cfg_data3_rd_ack)
        begin
        cfg_data3_wait_n = 0;
        end
        cfg_data3_rd_stb = 1;
      end
    endcase
  end
always @(posedge clk or negedge reset_n)
  begin
    if(~reset_n)
    sm_cfg_data3_state <= #1 st_sm_cfg_data3_idle;
    else
    sm_cfg_data3_state <= #1 nxt_sm_cfg_data3_state;
  end
always @*
  begin
    cfg_data3_wr_data = rf_wr_data;
    cfg_data3 = cfg_data3_rd_data;
  end
// status: cfg_status
endmodule

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Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] [app_localcfg/] [lcfg_cfgo_regs.v] - Blame information for rev 101

Line No.	Rev	Author	Line
1	101	ghutchis	`module lcfg_cfgo_regs (`
2			clk,reset_n,rf_irdy,rf_trdy,rf_write,rf_addr,rf_wr_data,rf_rd_data,cfg_addr0,cfg_addr1,cfg_data0_wr_stb,cfg_data0_rd_stb,cfg_data0_wr_data,cfg_data0_rd_data,cfg_data0_rd_ack,cfg_data0_wr_ack,cfg_data1_wr_stb,cfg_data1_rd_stb,cfg_data1_wr_data,cfg_data1_rd_data,cfg_data1_rd_ack,cfg_data1_wr_ack,cfg_data2_wr_stb,cfg_data2_rd_stb,cfg_data2_wr_data,cfg_data2_rd_data,cfg_data2_rd_ack,cfg_data2_wr_ack,cfg_data3_wr_stb,cfg_data3_rd_stb,cfg_data3_wr_data,cfg_data3_rd_data,cfg_data3_rd_ack,cfg_data3_wr_ack,cfg_status);
3			`input clk;`
4			`input reset_n;`
5			`input rf_irdy;`
6			`output rf_trdy;`
7			`input rf_write;`
8			`input [3:0] rf_addr;`
9			`input [7:0] rf_wr_data;`
10			`output [7:0] rf_rd_data;`
11			`output [7:0] cfg_addr0;`
12			`output [7:0] cfg_addr1;`
13			`output cfg_data0_wr_stb;`
14			`output cfg_data0_rd_stb;`
15			`output [7:0] cfg_data0_wr_data;`
16			`input [7:0] cfg_data0_rd_data;`
17			`input cfg_data0_rd_ack;`
18			`input cfg_data0_wr_ack;`
19			`output cfg_data1_wr_stb;`
20			`output cfg_data1_rd_stb;`
21			`output [7:0] cfg_data1_wr_data;`
22			`input [7:0] cfg_data1_rd_data;`
23			`input cfg_data1_rd_ack;`
24			`input cfg_data1_wr_ack;`
25			`output cfg_data2_wr_stb;`
26			`output cfg_data2_rd_stb;`
27			`output [7:0] cfg_data2_wr_data;`
28			`input [7:0] cfg_data2_rd_data;`
29			`input cfg_data2_rd_ack;`
30			`input cfg_data2_wr_ack;`
31			`output cfg_data3_wr_stb;`
32			`output cfg_data3_rd_stb;`
33			`output [7:0] cfg_data3_wr_data;`
34			`input [7:0] cfg_data3_rd_data;`
35			`input cfg_data3_rd_ack;`
36			`input cfg_data3_wr_ack;`
37			`input [7:0] cfg_status;`
38			`reg [7:0] rf_rd_data;`
39			`reg nxt_rf_trdy;`
40			`reg rf_trdy;`
41			`reg [7:0] cfg_addr0;`
42			`reg [7:0] nxt_cfg_addr0;`
43			`reg cfg_addr0_rd_sel;`
44			`reg cfg_addr0_wr_sel;`
45			`reg [7:0] cfg_addr1;`
46			`reg [7:0] nxt_cfg_addr1;`
47			`reg cfg_addr1_rd_sel;`
48			`reg cfg_addr1_wr_sel;`
49			`reg cfg_data0_rd_sel;`
50			`reg cfg_data0_wr_sel;`
51			`reg cfg_data0_rd_stb;`
52			`reg cfg_data0_wr_stb;`
53			`reg cfg_data0_wait_n;`
54			`reg [7:0] cfg_data0;`
55			`reg [7:0] cfg_data0_wr_data;`
56			`reg [1:0] sm_cfg_data0_state;`
57			`reg [1:0] nxt_sm_cfg_data0_state;`
58			`reg cfg_data1_rd_sel;`
59			`reg cfg_data1_wr_sel;`
60			`reg cfg_data1_rd_stb;`
61			`reg cfg_data1_wr_stb;`
62			`reg cfg_data1_wait_n;`
63			`reg [7:0] cfg_data1;`
64			`reg [7:0] cfg_data1_wr_data;`
65			`reg [1:0] sm_cfg_data1_state;`
66			`reg [1:0] nxt_sm_cfg_data1_state;`
67			`reg cfg_data2_rd_sel;`
68			`reg cfg_data2_wr_sel;`
69			`reg cfg_data2_rd_stb;`
70			`reg cfg_data2_wr_stb;`
71			`reg cfg_data2_wait_n;`
72			`reg [7:0] cfg_data2;`
73			`reg [7:0] cfg_data2_wr_data;`
74			`reg [1:0] sm_cfg_data2_state;`
75			`reg [1:0] nxt_sm_cfg_data2_state;`
76			`reg cfg_data3_rd_sel;`
77			`reg cfg_data3_wr_sel;`
78			`reg cfg_data3_rd_stb;`
79			`reg cfg_data3_wr_stb;`
80			`reg cfg_data3_wait_n;`
81			`reg [7:0] cfg_data3;`
82			`reg [7:0] cfg_data3_wr_data;`
83			`reg [1:0] sm_cfg_data3_state;`
84			`reg [1:0] nxt_sm_cfg_data3_state;`
85			`reg cfg_status_rd_sel;`
86			`always @*`
87			`begin`
88			`cfg_addr0_rd_sel = (rf_addr[3:0] == 0) & rf_irdy & !rf_write;`
89			`cfg_addr0_wr_sel = (rf_addr[3:0] == 0) & rf_irdy & rf_write;`
90
91			`cfg_addr1_rd_sel = (rf_addr[3:0] == 1) & rf_irdy & !rf_write;`
92			`cfg_addr1_wr_sel = (rf_addr[3:0] == 1) & rf_irdy & rf_write;`
93
94			`cfg_data0_rd_sel = (rf_addr[3:0] == 2) & rf_irdy & !rf_write;`
95			`cfg_data0_wr_sel = (rf_addr[3:0] == 2) & rf_irdy & rf_write;`
96
97			`cfg_data1_rd_sel = (rf_addr[3:0] == 3) & rf_irdy & !rf_write;`
98			`cfg_data1_wr_sel = (rf_addr[3:0] == 3) & rf_irdy & rf_write;`
99
100			`cfg_data2_rd_sel = (rf_addr[3:0] == 4) & rf_irdy & !rf_write;`
101			`cfg_data2_wr_sel = (rf_addr[3:0] == 4) & rf_irdy & rf_write;`
102
103			`cfg_data3_rd_sel = (rf_addr[3:0] == 5) & rf_irdy & !rf_write;`
104			`cfg_data3_wr_sel = (rf_addr[3:0] == 5) & rf_irdy & rf_write;`
105
106			`cfg_status_rd_sel = (rf_addr[3:0] == 6) & rf_irdy & !rf_write;`
107			`end`
108			`always @*`
109			`begin`
110			`case (1'b1)`
111			`cfg_addr0_rd_sel : rf_rd_data = cfg_addr0;`
112			`cfg_addr1_rd_sel : rf_rd_data = cfg_addr1;`
113			`cfg_data0_rd_sel : rf_rd_data = cfg_data0;`
114			`cfg_data1_rd_sel : rf_rd_data = cfg_data1;`
115			`cfg_data2_rd_sel : rf_rd_data = cfg_data2;`
116			`cfg_data3_rd_sel : rf_rd_data = cfg_data3;`
117			`cfg_status_rd_sel : rf_rd_data = cfg_status;`
118			`default : rf_rd_data = 8'b0;`
119			`endcase`
120			`end`
121			`always @*`
122			`begin`
123			`if (rf_trdy) nxt_rf_trdy = 0;`
124			`else if (rf_irdy) nxt_rf_trdy = cfg_data0_wait_n & cfg_data1_wait_n & cfg_data2_wait_n & cfg_data3_wait_n;`
125			`else nxt_rf_trdy = 0;`
126			`end`
127			`always @(posedge clk or negedge reset_n)`
128			`begin`
129			`if (~reset_n) rf_trdy <= #1 0;`
130			`else rf_trdy <= #1 nxt_rf_trdy;`
131			`end`
132			`// config: cfg_addr0`
133			`always @*`
134			`begin`
135			`if (cfg_addr0_wr_sel) nxt_cfg_addr0 = rf_wr_data;`
136			`else nxt_cfg_addr0 = cfg_addr0;`
137			`end`
138			`always @(posedge clk or negedge reset_n)`
139			`begin`
140			`if (~reset_n) cfg_addr0 <= #1 8'h0;`
141			`else cfg_addr0 <= #1 nxt_cfg_addr0;`
142			`end`
143			`// config: cfg_addr1`
144			`always @*`
145			`begin`
146			`if (cfg_addr1_wr_sel) nxt_cfg_addr1 = rf_wr_data;`
147			`else nxt_cfg_addr1 = cfg_addr1;`
148			`end`
149			`always @(posedge clk or negedge reset_n)`
150			`begin`
151			`if (~reset_n) cfg_addr1 <= #1 8'h0;`
152			`else cfg_addr1 <= #1 nxt_cfg_addr1;`
153			`end`
154			`// state machine sm_cfg_data0`
155			`parameter st_sm_cfg_data0_w_clear = 0;`
156			`parameter st_sm_cfg_data0_idle = 1;`
157			`parameter st_sm_cfg_data0_wr_req = 2;`
158			`parameter st_sm_cfg_data0_rd_req = 3;`
159			`always @*`
160			`begin`
161			`cfg_data0_rd_stb = 0;`
162			`cfg_data0_wr_stb = 0;`
163			`cfg_data0_wait_n = 1;`
164			`nxt_sm_cfg_data0_state = sm_cfg_data0_state;`
165			`case (sm_cfg_data0_state)`
166			`st_sm_cfg_data0_w_clear :`
167			`begin`
168			`if (~(cfg_data0_rd_sel \| cfg_data0_wr_sel))`
169			`begin`
170			`nxt_sm_cfg_data0_state = st_sm_cfg_data0_idle;`
171			`end`
172			`end`
173			`st_sm_cfg_data0_idle :`
174			`begin`
175			`if (cfg_data0_rd_sel)`
176			`begin`
177			`nxt_sm_cfg_data0_state = st_sm_cfg_data0_rd_req;`
178			`cfg_data0_wait_n = 0;`
179			`end`
180			`else if (cfg_data0_wr_sel)`
181			`begin`
182			`nxt_sm_cfg_data0_state = st_sm_cfg_data0_wr_req;`
183			`cfg_data0_wait_n = 0;`
184			`end`
185			`end`
186			`st_sm_cfg_data0_wr_req :`
187			`begin`
188			`if (cfg_data0_wr_ack)`
189			`begin`
190			`nxt_sm_cfg_data0_state = st_sm_cfg_data0_w_clear;`
191			`end`
192			`else if (!cfg_data0_wr_ack)`
193			`begin`
194			`cfg_data0_wait_n = 0;`
195			`end`
196			`cfg_data0_wr_stb = 1;`
197			`end`
198			`st_sm_cfg_data0_rd_req :`
199			`begin`
200			`if (cfg_data0_rd_ack)`
201			`begin`
202			`nxt_sm_cfg_data0_state = st_sm_cfg_data0_w_clear;`
203			`end`
204			`else if (!cfg_data0_rd_ack)`
205			`begin`
206			`cfg_data0_wait_n = 0;`
207			`end`
208			`cfg_data0_rd_stb = 1;`
209			`end`
210			`endcase`
211			`end`
212			`always @(posedge clk or negedge reset_n)`
213			`begin`
214			`if(~reset_n)`
215			`sm_cfg_data0_state <= #1 st_sm_cfg_data0_idle;`
216			`else`
217			`sm_cfg_data0_state <= #1 nxt_sm_cfg_data0_state;`
218			`end`
219			`always @*`
220			`begin`
221			`cfg_data0_wr_data = rf_wr_data;`
222			`cfg_data0 = cfg_data0_rd_data;`
223			`end`
224			`// state machine sm_cfg_data1`
225			`parameter st_sm_cfg_data1_w_clear = 0;`
226			`parameter st_sm_cfg_data1_idle = 1;`
227			`parameter st_sm_cfg_data1_wr_req = 2;`
228			`parameter st_sm_cfg_data1_rd_req = 3;`
229			`always @*`
230			`begin`
231			`cfg_data1_rd_stb = 0;`
232			`cfg_data1_wr_stb = 0;`
233			`cfg_data1_wait_n = 1;`
234			`nxt_sm_cfg_data1_state = sm_cfg_data1_state;`
235			`case (sm_cfg_data1_state)`
236			`st_sm_cfg_data1_w_clear :`
237			`begin`
238			`if (~(cfg_data1_rd_sel \| cfg_data1_wr_sel))`
239			`begin`
240			`nxt_sm_cfg_data1_state = st_sm_cfg_data1_idle;`
241			`end`
242			`end`
243			`st_sm_cfg_data1_idle :`
244			`begin`
245			`if (cfg_data1_rd_sel)`
246			`begin`
247			`nxt_sm_cfg_data1_state = st_sm_cfg_data1_rd_req;`
248			`cfg_data1_wait_n = 0;`
249			`end`
250			`else if (cfg_data1_wr_sel)`
251			`begin`
252			`nxt_sm_cfg_data1_state = st_sm_cfg_data1_wr_req;`
253			`cfg_data1_wait_n = 0;`
254			`end`
255			`end`
256			`st_sm_cfg_data1_wr_req :`
257			`begin`
258			`if (cfg_data1_wr_ack)`
259			`begin`
260			`nxt_sm_cfg_data1_state = st_sm_cfg_data1_w_clear;`
261			`end`
262			`else if (!cfg_data1_wr_ack)`
263			`begin`
264			`cfg_data1_wait_n = 0;`
265			`end`
266			`cfg_data1_wr_stb = 1;`
267			`end`
268			`st_sm_cfg_data1_rd_req :`
269			`begin`
270			`if (cfg_data1_rd_ack)`
271			`begin`
272			`nxt_sm_cfg_data1_state = st_sm_cfg_data1_w_clear;`
273			`end`
274			`else if (!cfg_data1_rd_ack)`
275			`begin`
276			`cfg_data1_wait_n = 0;`
277			`end`
278			`cfg_data1_rd_stb = 1;`
279			`end`
280			`endcase`
281			`end`
282			`always @(posedge clk or negedge reset_n)`
283			`begin`
284			`if(~reset_n)`
285			`sm_cfg_data1_state <= #1 st_sm_cfg_data1_idle;`
286			`else`
287			`sm_cfg_data1_state <= #1 nxt_sm_cfg_data1_state;`
288			`end`
289			`always @*`
290			`begin`
291			`cfg_data1_wr_data = rf_wr_data;`
292			`cfg_data1 = cfg_data1_rd_data;`
293			`end`
294			`// state machine sm_cfg_data2`
295			`parameter st_sm_cfg_data2_w_clear = 0;`
296			`parameter st_sm_cfg_data2_idle = 1;`
297			`parameter st_sm_cfg_data2_wr_req = 2;`
298			`parameter st_sm_cfg_data2_rd_req = 3;`
299			`always @*`
300			`begin`
301			`cfg_data2_rd_stb = 0;`
302			`cfg_data2_wr_stb = 0;`
303			`cfg_data2_wait_n = 1;`
304			`nxt_sm_cfg_data2_state = sm_cfg_data2_state;`
305			`case (sm_cfg_data2_state)`
306			`st_sm_cfg_data2_w_clear :`
307			`begin`
308			`if (~(cfg_data2_rd_sel \| cfg_data2_wr_sel))`
309			`begin`
310			`nxt_sm_cfg_data2_state = st_sm_cfg_data2_idle;`
311			`end`
312			`end`
313			`st_sm_cfg_data2_idle :`
314			`begin`
315			`if (cfg_data2_rd_sel)`
316			`begin`
317			`nxt_sm_cfg_data2_state = st_sm_cfg_data2_rd_req;`
318			`cfg_data2_wait_n = 0;`
319			`end`
320			`else if (cfg_data2_wr_sel)`
321			`begin`
322			`nxt_sm_cfg_data2_state = st_sm_cfg_data2_wr_req;`
323			`cfg_data2_wait_n = 0;`
324			`end`
325			`end`
326			`st_sm_cfg_data2_wr_req :`
327			`begin`
328			`if (cfg_data2_wr_ack)`
329			`begin`
330			`nxt_sm_cfg_data2_state = st_sm_cfg_data2_w_clear;`
331			`end`
332			`else if (!cfg_data2_wr_ack)`
333			`begin`
334			`cfg_data2_wait_n = 0;`
335			`end`
336			`cfg_data2_wr_stb = 1;`
337			`end`
338			`st_sm_cfg_data2_rd_req :`
339			`begin`
340			`if (cfg_data2_rd_ack)`
341			`begin`
342			`nxt_sm_cfg_data2_state = st_sm_cfg_data2_w_clear;`
343			`end`
344			`else if (!cfg_data2_rd_ack)`
345			`begin`
346			`cfg_data2_wait_n = 0;`
347			`end`
348			`cfg_data2_rd_stb = 1;`
349			`end`
350			`endcase`
351			`end`
352			`always @(posedge clk or negedge reset_n)`
353			`begin`
354			`if(~reset_n)`
355			`sm_cfg_data2_state <= #1 st_sm_cfg_data2_idle;`
356			`else`
357			`sm_cfg_data2_state <= #1 nxt_sm_cfg_data2_state;`
358			`end`
359			`always @*`
360			`begin`
361			`cfg_data2_wr_data = rf_wr_data;`
362			`cfg_data2 = cfg_data2_rd_data;`
363			`end`
364			`// state machine sm_cfg_data3`
365			`parameter st_sm_cfg_data3_w_clear = 0;`
366			`parameter st_sm_cfg_data3_idle = 1;`
367			`parameter st_sm_cfg_data3_wr_req = 2;`
368			`parameter st_sm_cfg_data3_rd_req = 3;`
369			`always @*`
370			`begin`
371			`cfg_data3_rd_stb = 0;`
372			`cfg_data3_wr_stb = 0;`
373			`cfg_data3_wait_n = 1;`
374			`nxt_sm_cfg_data3_state = sm_cfg_data3_state;`
375			`case (sm_cfg_data3_state)`
376			`st_sm_cfg_data3_w_clear :`
377			`begin`
378			`if (~(cfg_data3_rd_sel \| cfg_data3_wr_sel))`
379			`begin`
380			`nxt_sm_cfg_data3_state = st_sm_cfg_data3_idle;`
381			`end`
382			`end`
383			`st_sm_cfg_data3_idle :`
384			`begin`
385			`if (cfg_data3_rd_sel)`
386			`begin`
387			`nxt_sm_cfg_data3_state = st_sm_cfg_data3_rd_req;`
388			`cfg_data3_wait_n = 0;`
389			`end`
390			`else if (cfg_data3_wr_sel)`
391			`begin`
392			`nxt_sm_cfg_data3_state = st_sm_cfg_data3_wr_req;`
393			`cfg_data3_wait_n = 0;`
394			`end`
395			`end`
396			`st_sm_cfg_data3_wr_req :`
397			`begin`
398			`if (cfg_data3_wr_ack)`
399			`begin`
400			`nxt_sm_cfg_data3_state = st_sm_cfg_data3_w_clear;`
401			`end`
402			`else if (!cfg_data3_wr_ack)`
403			`begin`
404			`cfg_data3_wait_n = 0;`
405			`end`
406			`cfg_data3_wr_stb = 1;`
407			`end`
408			`st_sm_cfg_data3_rd_req :`
409			`begin`
410			`if (cfg_data3_rd_ack)`
411			`begin`
412			`nxt_sm_cfg_data3_state = st_sm_cfg_data3_w_clear;`
413			`end`
414			`else if (!cfg_data3_rd_ack)`
415			`begin`
416			`cfg_data3_wait_n = 0;`
417			`end`
418			`cfg_data3_rd_stb = 1;`
419			`end`
420			`endcase`
421			`end`
422			`always @(posedge clk or negedge reset_n)`
423			`begin`
424			`if(~reset_n)`
425			`sm_cfg_data3_state <= #1 st_sm_cfg_data3_idle;`
426			`else`
427			`sm_cfg_data3_state <= #1 nxt_sm_cfg_data3_state;`
428			`end`
429			`always @*`
430			`begin`
431			`cfg_data3_wr_data = rf_wr_data;`
432			`cfg_data3 = cfg_data3_rd_data;`
433			`end`
434			`// status: cfg_status`
435			`endmodule`