OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [tests/] [ivec_flags.ast] - Blame information for rev 99

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 99 ghutchis
; test of interrupt vector flags
2
;
3
; initializes a memory region and then transfers that region
4
; to an accumulator
5
 
6
    .module otir
7
 
8
;--------------------------------------------------------
9
; special function registers
10
;--------------------------------------------------------
11
_sim_ctl_port   =       0x0080
12
_msg_port       =       0x0081
13
_timeout_port   =       0x0082
14
_max_timeout_low        =       0x0083
15
_max_timeout_high       =       0x0084
16
_intr_cntdwn    =       0x0090
17
_cksum_value    =       0x0091
18
_cksum_accum    =       0x0092
19
_inc_on_read    =       0x0093
20
 
21
    .area INIT (ABS)
22
    .org  0
23
 
24
    jp      init
25
 
26
 
27
init:
28
    ld      sp, #0xffff
29
 
30
    ;--------------------------------------------------
31
    ; test S flag
32
 
33
    ; test for s set on negative values
34
    ld      a, #0xff
35
    ld      i, a
36
    ld      a, i   ; S should be set
37
    jp      p, test_fail
38
 
39
    ld      a, #0xff
40
    ld      r, a
41
    ld      a, r   ; S should be set
42
    jp      p, test_fail
43
 
44
    ; test for s clear on positive values
45
    ld      a, #0x20
46
    ld      i, a
47
    ld      a, i   ; S should be clear
48
    jp      m, test_fail
49
 
50
    ; test for s clear on positive values
51
    ld      a, #0x20
52
    ld      r, a
53
    ld      a, r   ; S should be clear
54
    jp      m, test_fail
55
 
56
 
57
    ;--------------------------------------------------
58
    ; test Z flag
59
 
60
    ; test for z set on zero values
61
    ld      a, #0
62
    ld      i, a
63
    ld      a, i   ; S should be set
64
    jp      nz, test_fail
65
 
66
    ld      a, #0
67
    ld      r, a
68
    ld      a, r   ; S should be set
69
    jp      nz, test_fail
70
 
71
    ; test for s clear on positive values
72
    ld      a, #0x20
73
    ld      i, a
74
    ld      a, i   ; S should be clear
75
    jp      z, test_fail
76
 
77
    ; test for s clear on positive values
78
    ld      a, #0x20
79
    ld      r, a
80
    ld      a, r   ; S should be clear
81
    jp      z, test_fail
82
 
83
    ;--------------------------------------------------
84
    ; test H flag
85
 
86
    ; by spec the H flag is not in the flags register,
87
    ; so this bit is difficult to test
88
 
89
    ;--------------------------------------------------
90
    ; test P/V flag
91
 
92
    ; TBD
93
 
94
    ;--------------------------------------------------
95
    ; test N flag
96
 
97
    neg               ; sets the N flag
98
    ld      a, i      ; clears N flag
99
    push    af
100
    pop     bc        ; N should be bit 4 of C
101
    ld      a, c
102
    and     #0x10
103
    jp      nz, test_fail
104
 
105
    neg               ; sets the N flag
106
    ld      a, r      ; clears N flag
107
    push    af
108
    pop     bc        ; N should be bit 4 of C
109
    ld      a, c
110
    and     #0x10
111
    jp      nz, test_fail
112
 
113
    ;--------------------------------------------------
114
    ; test C flag
115
    ; should not be affected by this op
116
 
117
    scf
118
    ld      a, i
119
    ld      a, r
120
    jp      nc, test_fail
121
 
122
    ccf
123
    ld      a, i
124
    ld      a, r
125
    jp      c, test_fail
126
 
127
test_pass:
128
    ;; finish simulation with test passed
129
    ld      a, #1
130
    out     (_sim_ctl_port), a
131
    halt
132
 
133
test_fail:
134
    ld      a, #2
135
    out     (_sim_ctl_port), a
136
    ret
137
 
138
reset_timeout:
139
    ld      a, #2
140
    out     (_timeout_port), a
141
    ret
142
 
143
    .org    0x8000
144
 
145
dbuf:
146
    .ds     256
147
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.