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https://opencores.org/ocsvn/uart16550/uart16550/trunk
[/] [uart16550/] [web_uploads/] [index.shtml] - Blame information for rev 108
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<!--# set var="title" value="uart16550 core page" -->
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<!--# include virtual="/ssi/ssi_start.shtml" -->
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<b><font size=+2 face="Helvetica, Arial"
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color=#bf0000>Project Name: uart16550 core</font></b>
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<p>
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<font size=+1><b>Description</b></font>
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<P>
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uart16550 is a 16550 compatible (mostly) UART core.
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<BR>
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<p>
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<!--Block diagram ...-->
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<p>
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The bus interface is WISHBONE SoC bus Rev. B.<BR>
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<p>
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Features all the standard options of the 16550 UART:<BR>
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FIFO based operation, interrupt requests and other.
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<p>
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The datasheet can be downloaded from the CVS tree along with the source code.
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<p>
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<font size=+1><B>Current Status</B></font><p>
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[Aug 2001]<br>
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Core updated and some more bugs fixed.<BR>
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It is now being verified more thoroughly but it is mostly usable.<P>
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[27.05.2001]<br>
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Documentation and core code are updated.<br>
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[17.05.2001]:
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<ul>
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<li>The core is finished unless more bugs are found.</li>
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<li>The test bench is very basic yet and is asking for your help to expand it. :-)</li>
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</ul>
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<p>Maintainer(s):
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<ul>Jacob Gorban (<a href="mailto:gorban@opencores.org_NOSPAM">gorban@opencores.org_NOSPAM)</a></ul>
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<p>Mailing-list:
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<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>
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