OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [baud_gen.v] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 motilito
//---------------------------------------------------------------------------------------
2
// baud rate generator for uart 
3
//
4
// this module has been changed to receive the baud rate dividing counter from registers.
5
// the two registers should be calculated as follows:
6
// first register:
7
//              baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
8
// second register:
9
//              baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq 
10 3 motilito
//
11 2 motilito
//---------------------------------------------------------------------------------------
12
 
13
module baud_gen
14
(
15
        clock, reset,
16
        ce_16, baud_freq, baud_limit
17
);
18
//---------------------------------------------------------------------------------------
19
// modules inputs and outputs 
20
input                   clock;          // global clock input 
21
input                   reset;          // global reset input 
22
output                  ce_16;          // baud rate multiplyed by 16 
23
input   [11:0]   baud_freq;      // baud rate setting registers - see header description 
24
input   [15:0]   baud_limit;
25
 
26
// internal registers 
27
reg ce_16;
28
reg [15:0]       counter;
29
//---------------------------------------------------------------------------------------
30
// module implementation 
31
// baud divider counter  
32
always @ (posedge clock or posedge reset)
33
begin
34
        if (reset)
35
                counter <= 16'b0;
36
        else if (counter >= baud_limit)
37
                counter <= counter - baud_limit;
38
        else
39
                counter <= counter + baud_freq;
40
end
41
 
42
// clock divider output 
43
always @ (posedge clock or posedge reset)
44
begin
45
        if (reset)
46
                ce_16 <= 1'b0;
47
        else if (counter >= baud_limit)
48
                ce_16 <= 1'b1;
49
        else
50
                ce_16 <= 1'b0;
51
end
52
 
53
endmodule
54
//---------------------------------------------------------------------------------------
55
//                                              Th.. Th.. Th.. Thats all folks !!!
56
//---------------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.