OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_tx.v] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 motilito
//---------------------------------------------------------------------------------------
2
// uart transmit module  
3
//
4
//---------------------------------------------------------------------------------------
5
 
6
module uart_tx
7
(
8
        clock, reset,
9
        ce_16, tx_data, new_tx_data,
10
        ser_out, tx_busy
11
);
12
//---------------------------------------------------------------------------------------
13
// modules inputs and outputs 
14
input                   clock;                  // global clock input 
15
input                   reset;                  // global reset input 
16
input                   ce_16;                  // baud rate multiplyed by 16 - generated by baud module 
17
input   [7:0]    tx_data;                // data byte to transmit 
18
input                   new_tx_data;    // asserted to indicate that there is a new data byte for transmission 
19
output                  ser_out;                // serial data output 
20
output                  tx_busy;                // signs that transmitter is busy 
21
 
22
// internal wires 
23
wire ce_1;              // clock enable at bit rate 
24
 
25
// internal registers 
26
reg ser_out;
27
reg tx_busy;
28
reg [3:0]        count16;
29
reg [3:0]        bit_count;
30
reg [8:0]        data_buf;
31
//---------------------------------------------------------------------------------------
32
// module implementation 
33
// a counter to count 16 pulses of ce_16 to generate the ce_1 pulse 
34
always @ (posedge clock or posedge reset)
35
begin
36
        if (reset)
37
                count16 <= 4'b0;
38
        else if (tx_busy & ce_16)
39
                count16 <= count16 + 4'b1;
40
        else if (~tx_busy)
41
                count16 <= 4'b0;
42
end
43
 
44
// ce_1 pulse indicating output data bit should be updated 
45
assign ce_1 = (count16 == 4'b1111) & ce_16;
46
 
47
// tx_busy flag 
48
always @ (posedge clock or posedge reset)
49
begin
50
        if (reset)
51
                tx_busy <= 1'b0;
52
        else if (~tx_busy & new_tx_data)
53
                tx_busy <= 1'b1;
54 9 motilito
        else if (tx_busy & (bit_count == 4'h9) & ce_1)
55 2 motilito
                tx_busy <= 1'b0;
56
end
57
 
58
// output bit counter 
59
always @ (posedge clock or posedge reset)
60
begin
61
        if (reset)
62
                bit_count <= 4'h0;
63
        else if (tx_busy & ce_1)
64
                bit_count <= bit_count + 4'h1;
65
        else if (~tx_busy)
66
                bit_count <= 4'h0;
67
end
68
 
69
// data shift register 
70
always @ (posedge clock or posedge reset)
71
begin
72
        if (reset)
73
                data_buf <= 9'b0;
74
        else if (~tx_busy)
75
                data_buf <= {tx_data, 1'b0};
76
        else if (tx_busy & ce_1)
77
                data_buf <= {1'b1, data_buf[8:1]};
78
end
79
 
80
// output data bit 
81
always @ (posedge clock or posedge reset)
82
begin
83
        if (reset)
84
                ser_out <= 1'b1;
85
        else if (tx_busy)
86
                ser_out <= data_buf[0];
87
        else
88
                ser_out <= 1'b1;
89
end
90
 
91
endmodule
92
//---------------------------------------------------------------------------------------
93
//                                              Th.. Th.. Th.. Thats all folks !!!
94
//---------------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.