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[/] [uart2bus/] [trunk/] [vhdl/] [bench/] [helpers/] [regFileModel.vhd] - Blame information for rev 13

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-----------------------------------------------------------------------------------------
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-- register file model as a simple memory 
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--
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-----------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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entity regFileModel is
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  port ( -- global signals
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         clr        : in  std_logic;                     -- global reset input
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         clk        : in  std_logic;                     -- global clock input
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         -- internal bus to register file
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         intAddress : in  std_logic_vector(7 downto 0);  -- address bus to register file
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         intWrData  : in  std_logic_vector(7 downto 0);  -- write data to register file
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         intWrite   : in  std_logic;                     -- write control to register file
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         intRead    : in  std_logic;                     -- read control to register file
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         intRdData  : out std_logic_vector(7 downto 0)); -- data read from register file
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end regFileModel;
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architecture Behavioral of regFileModel is
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  type RAM is array (integer range <>)of std_logic_vector (7 downto 0);
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  signal regFile : RAM (0 to 255);
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  begin
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    -- register file write
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        for index in 0 to 255 loop
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          regFile(index) <= (others => '0');
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        end loop;
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      elsif (rising_edge(clk)) then
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        if (intWrite = '1') then
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          regFile(to_integer(unsigned(intAddress))) <= intWrData;
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        end if;
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      end if;
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    end process;
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    -- register file read
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        intRdData <= (others => '0');
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      elsif (rising_edge(clk)) then
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        if (intRead = '1') then
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          intRdData <= regFile(to_integer(unsigned(intAddress)));
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        end if;
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      end if;
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    end process;
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  end Behavioral;

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