OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [vhdl/] [sim/] [modelsim/] [uart2bus_bin_sim.tcl] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 smuller
set prj_home "../.."
2
set tb_home "$prj_home/bench"
3
set src_home "$prj_home/rtl"
4
set sim_home "$prj_home/sim/modelsim"
5
set wave_file "wave_uart2bus_bin.do"
6
set time "2500 us"
7
 
8
transcript file ""
9
transcript file $sim_home/transcript.log
10
 
11
if {[file exists $sim_home/work]} {
12
  file delete -force $sim_home/work
13
}
14
vlib $sim_home/work
15
vmap work $sim_home/work
16
 
17
vcom -work work $src_home/uart2BusTop_pkg.vhd
18
vcom -work work $src_home/uartTx.vhd
19
vcom -work work $src_home/uartRx.vhd
20
vcom -work work $src_home/baudGen.vhd
21
vcom -work work $src_home/uartTop.vhd
22
vcom -work work $src_home/uartParser.vhd
23
vcom -work work $src_home/uart2BusTop.vhd
24
 
25
vcom -work work $tb_home/helpers/helpers_pkg.vhd
26
vcom -work work $tb_home/helpers/regFileModel.vhd
27
vcom -work work $tb_home/uart2BusTop_bin_tb.vhd
28
 
29
onbreak {resume}
30
 
31
vsim -voptargs=+acc work.uart2BusTop_bin_tb(behavior)
32
 
33
do $sim_home/$wave_file
34
 
35
run $time
36
 
37
transcript file ""

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.