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[/] [uart2bus_testbench/] [trunk/] [rtl/] [uart_top.v] - Blame information for rev 2

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1 2 HanySalah
//---------------------------------------------------------------------------------------
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// uart top level module  
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//
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//---------------------------------------------------------------------------------------
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module uart_top
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(
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        // global signals 
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        clock, reset,
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        // uart serial signals 
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        ser_in, ser_out,
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        // transmit and receive internal interface signals 
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        rx_data, new_rx_data,
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        tx_data, new_tx_data, tx_busy,
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        // baud rate configuration register - see baud_gen.v for details 
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        baud_freq, baud_limit,
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        baud_clk
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);
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//---------------------------------------------------------------------------------------
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// modules inputs and outputs 
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input                   clock;                  // global clock input 
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input                   reset;                  // global reset input 
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input                   ser_in;                 // serial data input 
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output                  ser_out;                // serial data output 
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input   [7:0]    tx_data;                // data byte to transmit 
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input                   new_tx_data;    // asserted to indicate that there is a new data byte for transmission 
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output                  tx_busy;                // signs that transmitter is busy 
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output  [7:0]    rx_data;                // data byte received 
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output                  new_rx_data;    // signs that a new byte was received 
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input   [11:0]   baud_freq;      // baud rate setting registers - see header description 
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input   [15:0]   baud_limit;
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output                  baud_clk;
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// internal wires 
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wire ce_16;             // clock enable at bit rate 
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assign baud_clk = ce_16;
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//---------------------------------------------------------------------------------------
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// module implementation 
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// baud rate generator module 
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baud_gen baud_gen_1
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(
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        .clock(clock), .reset(reset),
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        .ce_16(ce_16), .baud_freq(baud_freq), .baud_limit(baud_limit)
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);
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// uart receiver 
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uart_rx uart_rx_1
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(
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        .clock(clock), .reset(reset),
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        .ce_16(ce_16), .ser_in(ser_in),
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        .rx_data(rx_data), .new_rx_data(new_rx_data)
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);
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// uart transmitter 
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uart_tx  uart_tx_1
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(
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        .clock(clock), .reset(reset),
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        .ce_16(ce_16), .tx_data(tx_data), .new_tx_data(new_tx_data),
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        .ser_out(ser_out), .tx_busy(tx_busy)
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);
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endmodule
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//---------------------------------------------------------------------------------------
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//                                              Th.. Th.. Th.. Thats all folks !!!
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//---------------------------------------------------------------------------------------

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