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[/] [uart2bus_testbench/] [trunk/] [tb/] [agent/] [driver/] [uart_driver.svh] - Blame information for rev 3

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Line No. Rev Author Line
1 3 HanySalah
//-------------------------------------------------------------------------------------------------
2 2 HanySalah
//
3 3 HanySalah
//                                     UART2BUS VERIFICATION
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//
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//-------------------------------------------------------------------------------------------------
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// CREATOR    : HANY SALAH
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// PROJECT    : UART2BUS UVM TEST BENCH
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// UNIT       : DRIVER
9 3 HanySalah
//-------------------------------------------------------------------------------------------------
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// TITLE      : UART DRIVER
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// DESCRIPTION: THIS DRIVER IS RESPONSIBLE FOR SETTING BFMS CONFIGURATIONS. ALSO DRIVING STIMULUS
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//              TO THE BFMS AND SENDING TRANSACTIONS TO SCOREBOARD.
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//-------------------------------------------------------------------------------------------------
14 2 HanySalah
// LOG DETAILS
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//-------------
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// VERSION      NAME        DATE        DESCRIPTION
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//    1       HANY SALAH    02012016    FILE CREATION
18 3 HanySalah
//    2       HANY SALAH    07012016    ADD INITIALIZE BFM METHOD
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//    3       HANY SALAH    17022016    IMPROVE BLOCK DESCRIPTION AND ADD COMMENTS
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//-------------------------------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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class uart_driver extends uvm_driver #(uart_transaction);
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27 3 HanySalah
  // Two Transaction Instances that are used to bring and clone the stimulus
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  uart_transaction      trans,_trans;
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  // Instance from Global UART Configuration
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  uart_config           _config;
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  // UART Interafce instance
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  virtual uart_interface  uart_inf;
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  // RF Interface instance
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  virtual rf_interface rf_inf;
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  // Arbiter Interface Instance
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  virtual uart_arbiter  arb_inf;
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42 3 HanySalah
  // Analysis Port to both scoreboard and driver
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  uvm_analysis_port #(uart_transaction)   drv_scbd_cov;
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  `uvm_component_utils(uart_driver)
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  function new (string name , uvm_component parent);
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    super.new(name,parent);
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  endfunction: new
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51 3 HanySalah
  // UVM Build Phase Declaration that includes locating instances and get interfaces handler from
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  // the configuration database
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  extern function void build_phase (uvm_phase phase);
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55 3 HanySalah
  // Both BFMs configurations setting and BFMs assignment are carried out through this UVM phase.
56 2 HanySalah
  extern function void end_of_elaboration_phase (uvm_phase phase);
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  extern task run_phase (uvm_phase phase);
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  // Actual drive data routine
61 3 HanySalah
  extern task drive_data ();
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  // initialize bfms
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  extern function void initialize_bfms (act_edge  _edge,
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                                        start_bit _bit,
66 3 HanySalah
                                        int enable,
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                                        int num_stop_bits,
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                                        int num_of_bits,
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                                        data_mode _datamode,
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                                        parity_mode _paritymode,
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                                        time _resp);
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endclass:uart_driver
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function void uart_driver::build_phase (uvm_phase phase);
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  super.build_phase(phase);
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  trans   = uart_transaction::type_id::create("trans");
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  _trans  = uart_transaction::type_id::create("_trans");
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  _config = uart_config::type_id::create("_config");
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  drv_scbd_cov = new("drv_scbd_cov",this);
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endfunction:build_phase
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function void uart_driver::end_of_elaboration_phase (uvm_phase phase);
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  if(!uvm_config_db#(uart_config)::get(this, "", "UART_CONFIGURATION", _config))
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    `uvm_fatal("NOCONFIGURATION",{"configuration instance must be set for: ",get_full_name(),"._config"});
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  if(!uvm_config_db#(virtual uart_interface)::get(this, "", "uart_inf", _config.uart_inf))
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      `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".uart_inf"});
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    uart_inf=_config.uart_inf;
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  if(!uvm_config_db#(virtual rf_interface)::get(this, "", "rf_inf", _config.rf_inf))
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      `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".rf_inf"});
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    rf_inf=_config.rf_inf;
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  if(!uvm_config_db#(virtual uart_arbiter)::get(this,"","arb_inf",_config.arb_inf))
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      `uvm_fatal("NOVIF",{"virtual interface must be set for:",get_full_name(),".arb_inf"})
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    arb_inf=_config.arb_inf;
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103 3 HanySalah
  initialize_bfms(_config._edge,
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              _config._start,
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              _config.use_false_data,
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              _config.num_stop_bits,
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              _config.num_of_bits,
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              _config._datamode,
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              _config._paritymode,
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              _config.response_time);
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112 2 HanySalah
endfunction:end_of_elaboration_phase
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function void uart_driver::initialize_bfms (act_edge  _edge,
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                                            start_bit _bit,
116 3 HanySalah
                                            int  enable,
117 2 HanySalah
                                            int num_stop_bits,
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                                            int num_of_bits,
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                                            data_mode _datamode,
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                                            parity_mode _paritymode,
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                                            time      _resp);
122 3 HanySalah
  uart_inf.set_configuration (_edge,_bit,num_stop_bits,num_of_bits,_datamode,_paritymode,_resp,enable);
123 2 HanySalah
endfunction:initialize_bfms
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task uart_driver::run_phase (uvm_phase phase);
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  forever
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    begin
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    seq_item_port.get_next_item(_trans);
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    $cast(trans,_trans.clone());
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    drv_scbd_cov.write(trans);
132 3 HanySalah
    drive_data();
133 2 HanySalah
    seq_item_port.item_done();
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    end
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endtask:run_phase
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137 3 HanySalah
task uart_driver::drive_data();
138 2 HanySalah
  uart_inf.wait_idle_time(trans.time_before*trans.scale);
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  uart_inf.set_event();
140 3 HanySalah
  if (trans._mode == text || trans._mode == wrong_mode_text)
141 2 HanySalah
    begin
142 3 HanySalah
    case(trans._command)
143 2 HanySalah
      read:
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        begin
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        /*fork
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        begin
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          if (trans._arbit == accept)
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            begin
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            arb_inf.accept_req();
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            end
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          else
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            begin
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            arb_inf.declain_req();
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            end
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        end
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        join_none*/
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        rf_inf.fill_byte (trans.address,
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                          trans._data[0]);
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        uart_inf.read_text_mode(trans._mode,
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                                trans.wrong_prefix,
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                                trans._chartype,
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                                trans._spacetype1,
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                                trans.space_wrong1,
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                                trans._eoltype,
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                                trans.eol_wrong,
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                                trans.address,
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                                trans.false_data[0],
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                                trans.false_data_en);
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170 2 HanySalah
        end
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      write:
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        begin
173 3 HanySalah
        /*fork
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        begin
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          if (trans._arbit == accept)
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            begin
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            arb_inf.accept_req();
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            end
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          else
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            begin
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            arb_inf.declain_req();
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            end
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        end
184 3 HanySalah
        join_none*/
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        uart_inf.write_text_mode(trans._mode,
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                                 trans.wrong_prefix,
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                                 trans._chartype,
188 2 HanySalah
                                 trans._spacetype1,
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                                 trans.space_wrong1,
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                                 trans._spacetype2,
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                                 trans.space_wrong2,
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                                 trans._eoltype,
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                                 trans.eol_wrong,
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                                 trans.address,
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                                 trans._data[0]);
196 3 HanySalah
 
197 2 HanySalah
        end
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      nop:
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        begin
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        `uvm_fatal("UNEXPECTED VALUE","NOP command value shouldn't be valued in text mode")
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        end
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      default:
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        begin
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        `uvm_fatal("wrong output", "wrong_mode")
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        end
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    endcase
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    end
208 3 HanySalah
  else if (trans._mode==binary || trans._mode==wrong_mode_bin)
209 2 HanySalah
    begin
210 3 HanySalah
    if (trans._command == read || trans._command == invalid_read)
211
      begin
212
      rf_inf.fill_block(trans.address,
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                        trans._data,
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                        trans.length_data);
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      uart_inf.read_binary_mode(trans._mode,
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                                trans.wrong_prefix,
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                                trans._command,
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                                trans._reqack,
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                                trans._reqinc,
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                                trans.length_data,
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                                trans.address,
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                                trans._data,
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                                trans.false_data,
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                                trans.false_data_en);
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      end
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    else if (trans._command == write || trans._command == invalid_write)
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      begin
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      uart_inf.write_binary_mode(trans._mode,
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                                 trans.wrong_prefix,
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                                 trans._command,
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                                 trans._reqack,
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                                 trans._reqinc,
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                                 trans.length_data,
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                                 trans.address,
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                                 trans._data);
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      end
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    else
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      begin
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      uart_inf.nop_command(trans._mode,
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                           trans.wrong_prefix,
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                           trans._reqack,
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                           trans._reqinc);
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      end
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245 2 HanySalah
    end
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  uart_inf.wait_idle_time(trans.time_after*trans.scale);
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endtask:drive_data

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