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URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [draft] - Blame information for rev 2

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Line No. Rev Author Line
1 2 HanySalah 
view wave
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add wave  \
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sim:/uart_top_tb/uart_inf/ser_in \
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sim:/uart_top_tb/uart_inf/ser_out \
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sim:/uart_top_tb/uart_inf/clock \
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sim:/uart_top_tb/uart_inf/start_trans \
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sim:/uart_top_tb/rf_inf/int_address \
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sim:/uart_top_tb/rf_inf/int_wr_data \
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sim:/uart_top_tb/rf_inf/int_write \
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sim:/uart_top_tb/rf_inf/int_rd_data \
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sim:/uart_top_tb/rf_inf/int_read \
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sim:/uart_top_tb/rf_inf/int_gnt \
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sim:/uart_top_tb/rf_inf/int_req

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