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//-----------------------------------------------------------------------------

//

//                             UART2BUS VERIFICATION

//

//-----------------------------------------------------------------------------

// CREATOR    : HANY SALAH

// PROJECT    : UART2BUS UVM TEST BENCH

// UNIT       : INTERFACE

//-----------------------------------------------------------------------------

// TITLE      : UART Interface

// DESCRIPTION: This

//-----------------------------------------------------------------------------

// LOG DETAILS

//-------------

// VERSION      NAME        DATE        DESCRIPTION

//    1       HANY SALAH    25122015    FILE CREATION

//-----------------------------------------------------------------------------

// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR

// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE

// CREATOR'S PERMISSION

//-----------------------------------------------------------------------------

`include "defin_lib.svh"

interface rf_interface (input bit clock,        // Global Clock Signal

                        input bit reset);       // Global Asynchronous Reset Signal

//--------------------------------

//

//   Register File Side Signals

//

//--------------------------------

  logic [15:0]   int_address;    // Address Bus To Register File

  logic [7:0]         int_wr_data;    // Write Data To Register File

  logic               int_write;      // Write Contorl To Register File

  logic [7:0]         int_rd_data;    // Read Data From Register File

  logic               int_read;       // Read Control To Register File

//--------------------------------

//

//  CONTROL SIGNALS

//

//--------------------------------

  logic               int_gnt;

  logic               int_req;

//--------------------------------

//

//   Internal Variables

//

//--------------------------------

  // Memory of 64K bytes as Register File

  byte       register_file [`mem_size-1:0];

//--------------------------------

//

//   Operation Blocks

//

//--------------------------------

  always

    begin

    @(posedge clock or posedge reset);

      begin

      if (reset)

        begin

        reset_mem();

        end

      else if (int_write)

        begin

        fill_byte(int_address,int_wr_data);

        end

      else if (int_read)

        begin

        int_rd_data = read_mem_data(int_address);

        end

      end

    end

//--------------------------------

//

//   Non Standard Routines

//

//--------------------------------

  // fill_byte routine is a function that fill only single byte in the register

  // file

function void fill_byte (bit [`size-1:0] address,

                         byte            data);

  register_file[address] = data;

endfunction:fill_byte

  // fill_block routine is a function that fill continuous block of locations

  // in the register file

function automatic void fill_block(bit [`size-1:0] address,

                                   ref byte data [],

                                   int unsigned block_length);

    for (int unsigned index = 0; index < block_length; index++)

      begin

      register_file[address+index] = data [index];

      end

endfunction:fill_block

  // reset_mem routine is a function that fill reset the register file to contents

  // zero

 function void reset_mem();

  for (int unsigned index = 0; index < `mem_size; index++)

    begin

    register_file[index] = 8'b0;

    end

endfunction:reset_mem

  // read_mem_data routine is a function that load bus with the data content

  function byte read_mem_data(bit [`size-1:0] address);

    return register_file[address];

  endfunction: read_mem_data

  task automatic read_block(input int unsigned data_length,

                            input bit [15:0] address,

                            ref byte data []);

    data = new [data_length];

    for (int unsigned index=0;index

      begin

      data[index] = read_mem_data(address+index);

      end

  endtask:read_block

  //-----------------------------------------

  //

  //        MONITOR ROUTINES

  //

  //-----------------------------------------

  task automatic capture_transaction (output bit[`size-1:0] address,

                                      ref byte data []);

    int index;

    index = 0;

    @(posedge int_gnt);

    while (int_gnt)

      begin

      @(posedge clock);

      if(index == 0)

        begin

        address = int_address;

        end

      if(int_read)

        begin

        data [index] = int_rd_data;

        end

      else if (int_write)

        begin

        data [index] = int_wr_data;

        end

      else

        begin

        $error("both int_write and int_read is inactive");

        end

      index++;

      end

  endtask:capture_transaction

endinterface:rf_interface