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URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [run.do] - Blame information for rev 2

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Line No. Rev Author Line
1 2 HanySalah
vlib work
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#vlog -novopt ../../../uvm-1.2/src/uvm.sv +incdir+../../../uvm-1.2/src/
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vlog -novopt interfaces/uart_interface.sv +incdir+../
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vlog -novopt interfaces/rf_interface.sv +incdir+../
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vlog -novopt interfaces/uart_arbiter.sv +incdir+../
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#vlog -novopt agent/agent_pkg.sv +incdir+agent/
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#vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver  +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+../../../uvm-1.2/src/
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vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver  +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+agent/monitor
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vlog -novopt env/env_pkg.sv +incdir+env +incdir+analysis
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#vlog -novopt env/env_pkg.sv +incdir+env +incdir+../../../uvm-1.2/src/
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vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+./ +incdir+../
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#vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+../../../uvm-1.2/src/ +incdir+./
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vlog ../rtl/uart_tx.v +incdir+../rtl
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vlog ../rtl/uart_rx.v +incdir+../rtl
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vlog ../rtl/baud_gen.v +incdir+../rtl
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vlog ../rtl/uart_top.v +incdir+../rtl
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vlog ../rtl/uart_parser.v +incdir+../rtl
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vlog ../rtl/uart2bus_top.v +incdir+../rtl
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vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl
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#vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+../../../uvm-1.2/src/
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vsim -novopt uart_top_tb
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view wave
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add wave  \
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sim:/uart_top_tb/uart_inf/ser_in \
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sim:/uart_top_tb/uart_inf/ser_out \
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sim:/uart_top_tb/uart_inf/serial_out \
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sim:/uart_top_tb/serial_out \
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sim:/uart_top_tb/uart_inf/clock \
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sim:/uart_top_tb/uart_inf/start_trans \
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sim:/uart_top_tb/rf_inf/int_address \
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sim:/uart_top_tb/rf_inf/int_wr_data \
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sim:/uart_top_tb/rf_inf/int_write \
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sim:/uart_top_tb/rf_inf/int_rd_data \
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sim:/uart_top_tb/rf_inf/int_read \
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sim:/uart_top_tb/rf_inf/int_gnt \
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sim:/uart_top_tb/rf_inf/int_req \
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sim:/uart_top_tb/dut/int_gnt \
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sim:/uart_top_tb/dut/int_req \
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sim:/uart_top_tb/dut/ser_in \
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sim:/uart_top_tb/dut/ser_out \
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sim:/uart_top_tb/dut/reset \
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sim:/uart_top_tb/dut/clock
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run -all
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#vsim i2c_top +UVM_CONFIG_DB_TRACE
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#run -all

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