OpenCores
URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [run_script.sh] - Blame information for rev 17

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 HanySalah
rm -rf work
2 17 HanySalah
rm -rf *.log
3
rm -rf transcript
4
rm -rf vsim.wlf
5
rm -rf vsim_stacktrace.vstf
6 15 HanySalah
vlib work
7
#------------------------------
8
# BFMs Compiling
9
#------------------------------
10
vlog -novopt interfaces/uart_interface.sv +incdir+../
11
vlog -novopt interfaces/rf_interface.sv +incdir+../
12
vlog -novopt interfaces/uart_arbiter.sv +incdir+../
13
#-----------------------------
14
# Agent Compiling
15
#------------------------------
16
vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver  +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+agent/monitor +incdir+agent/coverage
17
#-----------------------------
18
# Environment & Scoreboard Compiling
19
#------------------------------
20
vlog -novopt env/env_pkg.sv +incdir+env +incdir+analysis
21
#-----------------------------
22
# UART TEST Compiling
23
#------------------------------
24
vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+./ +incdir+../
25
#-----------------------------
26
# UART DUT Compiling
27
#------------------------------
28
vlog ../rtl/uart_tx.v +incdir+../rtl
29
vlog ../rtl/uart_rx.v +incdir+../rtl
30
vlog ../rtl/baud_gen.v +incdir+../rtl
31
vlog ../rtl/uart_top.v +incdir+../rtl
32
vlog ../rtl/uart_parser.v +incdir+../rtl
33
vlog ../rtl/uart2bus_top.v +incdir+../rtl
34
#-----------------------------
35
# UART Top Testbench Compiling
36
#------------------------------
37
vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl +UVM_TESTNAME=write_text_mode
38
#-----------------------------
39
# UART Top Testbench Simulation
40
#------------------------------
41
vsim -novopt +coverage -c uart_top_tb
42
#run -all

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.