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[/] [uart2bus_testbench/] [trunk/] [tb/] [test/] [uart_test.svh] - Blame information for rev 3

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Line No. Rev Author Line
1 3 HanySalah
//-------------------------------------------------------------------------------------------------
2 2 HanySalah
//
3
//                             UART2BUS VERIFICATION
4
//
5 3 HanySalah
//-------------------------------------------------------------------------------------------------
6 2 HanySalah
// CREATOR    : HANY SALAH
7
// PROJECT    : UART2BUS UVM TEST BENCH
8
// UNIT       : TEST
9 3 HanySalah
//-------------------------------------------------------------------------------------------------
10 2 HanySalah
// TITLE      : UART TEST
11 3 HanySalah
// DESCRIPTION: THIS COMPONENT INCLUDES THE MAIN TESTS THAT WILL BE FORCED TO THE DUT. IT INCLUDES
12
//              VIRTUAL BASE TEST FUNCTION THAT SHARES THE MOST COMMON ATTRIBUTES OF ALL TESTS.
13
//              THE TESTS IMPLEMENTED THROUGH BELOW ARE RELATED TO THE TESTBENCH SPECIFICATIONS
14
//              DOCUMENT. YOU CAN DOWNLOAD IT DIRECTLY THROUGH OPENCORES.COM OR FIND IT IN THE DOC
15
//              DIRECTORY.
16
//-------------------------------------------------------------------------------------------------
17 2 HanySalah
// LOG DETAILS
18
//-------------
19
// VERSION      NAME        DATE        DESCRIPTION
20
//    1       HANY SALAH    10012016    FILE CREATION
21 3 HanySalah
//    2       HANY SALAH    20012016    ADD BINARY MODE TESTS AND INVALID TESTS
22
//    3       HANY SALAH    12022016    IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
23
//-------------------------------------------------------------------------------------------------
24
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
25
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
26
//-------------------------------------------------------------------------------------------------
27
 
28
//  The base test class that includes the uvm printer and establish the whole environment.
29
//  It also responsible for setting the environment configurations described in details through the
30
//  testbench specifications document.
31
//  The environment configurations are set during the end of elaboration phase. It includes:
32
//    ----------------------------------------------------------------------------------------
33
//  - The active edge   : The active clock edge at which, the data is changed on the UART buses.
34
//                        It could be positive edge or negative edge.
35
//    ----------------------------------------------------------------------------------------
36
//  - The start bit     : Represent the sequence through which the byte is serialized; either to
37
//                        start with the most significant bit or the least significant bit.
38
//    ----------------------------------------------------------------------------------------
39
//  - The data format   : The data representation through the text commands either to be ASCII
40
//                        format or ordinary binary format.
41
//    ----------------------------------------------------------------------------------------
42
//  - The number of stop: The number of stop bits sent after the latest bit of each byte. It
43
//    bit(s)              would be either one or two bits
44
//    ----------------------------------------------------------------------------------------
45
//  - The number of bits: The number of bits within each transferred field. It would be either
46
//    in the field        7 or 8 bits per field.
47
//    ----------------------------------------------------------------------------------------
48
//  - The parity mode   : The used parity type of each field. It would be either no parity bit,
49
//                        odd parity or even parity.
50
//    ----------------------------------------------------------------------------------------
51
//  - The response time : Represent the maximum allowable time within which DUT should respond
52
//                        to the driven request.
53
//    ----------------------------------------------------------------------------------------
54
//  - The false data    : Enable force false data on the output port within the read command
55
//    enable              through the both modes; text or binary.
56
//    ----------------------------------------------------------------------------------------
57
virtual class uart_base_test extends uvm_test;
58
 
59 2 HanySalah
  uart_env          env;
60
 
61
  uvm_table_printer printer;
62
 
63
  uart_config       _config;
64
 
65
  `uvm_component_utils(uart_base_test)
66
 
67
  function new (string name,uvm_component parent);
68
    super.new(name,parent);
69
  endfunction:new
70
 
71
  function void build_phase (uvm_phase phase);
72
    super.build_phase(phase);
73
 
74
    env = uart_env::type_id::create("env",this);
75
 
76
    _config = uart_config::type_id::create("_config",this);
77
 
78
    uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
79
 
80
    printer = new();
81
    printer.knobs.depth = 3;
82
  endfunction:build_phase
83
 
84
  function void connect_phase (uvm_phase phase);
85
    super.connect_phase(phase);
86
  endfunction:connect_phase
87
 
88
  function void end_of_elaboration_phase (uvm_phase phase);
89
    super.end_of_elaboration_phase(phase);
90
    _config._edge         = pos_edge;
91
    _config._start        = lsb;
92
    _config._datamode     = ascii;
93
    _config.num_stop_bits = 1;
94
    _config.num_of_bits   = 8;
95
    _config._paritymode   = parity_off;
96 3 HanySalah
    _config.response_time = 8680;
97
    _config.use_false_data= no;
98 2 HanySalah
  endfunction:end_of_elaboration_phase
99
 
100
  task run_phase (uvm_phase phase);
101
    phase.phase_done.set_drain_time(this,5000);
102
  endtask:run_phase
103
endclass:uart_base_test
104
 
105 3 HanySalah
//-------------------------------------------------------------------------------------------------
106
//
107
//                          PURE TEXT MODE TESTS
108
//
109
//-------------------------------------------------------------------------------------------------
110 2 HanySalah
 
111 3 HanySalah
  //  This test apply thirteen successive tests of UART write request using text communication mode.
112
  //  Refer to test plan section in the testbench specifications document for more details.
113
  class write_text_mode extends uart_base_test;
114
 
115
    seq_1p1   seq1;
116
    seq_1p2   seq2;
117
    seq_1p3   seq3;
118
    seq_1p4   seq4;
119
    seq_1p5   seq5;
120
    seq_1p6   seq6;
121
    seq_1p7   seq7;
122
    seq_1p8   seq8;
123
    seq_1p9   seq9;
124
    seq_1p10  seq10;
125
    seq_1p11  seq11;
126
    seq_1p12  seq12;
127
    seq_1p13  seq13;
128 2 HanySalah
 
129 3 HanySalah
    `uvm_component_utils(write_text_mode)
130 2 HanySalah
 
131 3 HanySalah
    function new (string name,uvm_component parent);
132
      super.new(name,parent);
133
    endfunction:new
134 2 HanySalah
 
135 3 HanySalah
    function void build_phase (uvm_phase phase);
136
      super.build_phase (phase);
137
      seq1  = seq_1p1::type_id::create("seq1");
138
      seq2  = seq_1p2::type_id::create("seq2");
139
      seq3  = seq_1p3::type_id::create("seq3");
140
      seq4  = seq_1p4::type_id::create("seq4");
141
      seq5  = seq_1p5::type_id::create("seq5");
142
      seq6  = seq_1p6::type_id::create("seq6");
143
      seq7  = seq_1p7::type_id::create("seq7");
144
      seq8  = seq_1p8::type_id::create("seq8");
145
      seq9  = seq_1p9::type_id::create("seq9");
146
      seq10 = seq_1p10::type_id::create("seq10");
147
      seq11 = seq_1p11::type_id::create("seq11");
148
      seq12 = seq_1p12::type_id::create("seq12");
149
      seq13 = seq_1p13::type_id::create("seq13");
150
    endfunction:build_phase
151 2 HanySalah
 
152
 
153 3 HanySalah
    task run_phase (uvm_phase phase);
154
      super.run_phase(phase);
155
      phase.raise_objection(this);
156
      seq1.start(env.agent._seq,null);
157
      seq2.start(env.agent._seq,null);
158
      seq3.start(env.agent._seq,null);
159
      seq4.start(env.agent._seq,null);
160
      seq5.start(env.agent._seq,null);
161
      seq6.start(env.agent._seq,null);
162
      seq7.start(env.agent._seq,null);
163
      seq8.start(env.agent._seq,null);
164
      seq9.start(env.agent._seq,null);
165
      seq10.start(env.agent._seq,null);
166
      seq11.start(env.agent._seq,null);
167
      seq12.start(env.agent._seq,null);
168
      seq13.start(env.agent._seq,null);
169
      phase.drop_objection(this);
170
    endtask:run_phase
171
  endclass:write_text_mode
172 2 HanySalah
 
173 3 HanySalah
  //  This test apply thirteen successive tests of UART read request using text communication mode.
174
  //  Refer to test plan section in the testbench specifications document for more details.
175
  class read_text_mode extends uart_base_test;
176
 
177
    seq_2p1   seq1;
178
    seq_2p2   seq2;
179
    seq_2p3   seq3;
180
    seq_2p4   seq4;
181
    seq_2p5   seq5;
182
    seq_2p6   seq6;
183
    seq_2p7   seq7;
184
    seq_2p8   seq8;
185
    seq_2p9   seq9;
186
    seq_2p10  seq10;
187
    seq_2p11  seq11;
188
    seq_2p12  seq12;
189
    seq_2p13  seq13;
190 2 HanySalah
 
191
 
192 3 HanySalah
    `uvm_component_utils(read_text_mode)
193 2 HanySalah
 
194 3 HanySalah
    function new (string name,uvm_component parent);
195
      super.new(name,parent);
196
    endfunction:new
197 2 HanySalah
 
198 3 HanySalah
    function void build_phase (uvm_phase phase);
199
      super.build_phase(phase);
200
      seq1  = seq_2p1::type_id::create("seq1");
201
      seq2  = seq_2p2::type_id::create("seq2");
202
      seq3  = seq_2p3::type_id::create("seq3");
203
      seq4  = seq_2p4::type_id::create("seq4");
204
      seq5  = seq_2p5::type_id::create("seq5");
205
      seq6  = seq_2p6::type_id::create("seq6");
206
      seq7  = seq_2p7::type_id::create("seq7");
207
      seq8  = seq_2p8::type_id::create("seq8");
208
      seq9  = seq_2p9::type_id::create("seq9");
209
      seq10 = seq_2p10::type_id::create("seq10");
210
      seq11 = seq_2p11::type_id::create("seq11");
211
      seq12 = seq_2p12::type_id::create("seq12");
212
      seq13 = seq_2p13::type_id::create("seq13");
213
    endfunction:build_phase
214 2 HanySalah
 
215 3 HanySalah
    task run_phase (uvm_phase phase);
216
      super.run_phase(phase);
217
      phase.raise_objection(this);
218
      seq1.start(env.agent._seq,null);
219
      seq2.start(env.agent._seq,null);
220
      seq3.start(env.agent._seq,null);
221
      seq4.start(env.agent._seq,null);
222
      seq5.start(env.agent._seq,null);
223
      seq6.start(env.agent._seq,null);
224
      seq7.start(env.agent._seq,null);
225
      seq8.start(env.agent._seq,null);
226
      seq9.start(env.agent._seq,null);
227
      seq10.start(env.agent._seq,null);
228
      seq11.start(env.agent._seq,null);
229
      seq12.start(env.agent._seq,null);
230
      seq13.start(env.agent._seq,null);
231
      phase.drop_objection(this);
232
    endtask:run_phase
233
  endclass:read_text_mode
234 2 HanySalah
 
235 3 HanySalah
//-------------------------------------------------------------------------------------------------
236
//
237
//                          PURE BINARY MODE TESTS
238
//
239
//-------------------------------------------------------------------------------------------------
240 2 HanySalah
 
241 3 HanySalah
  //  This test apply six successive tests of UART nop request using binary communication mode.
242
  //  Refer to test plan section in the testbench specifications document for more details.
243
  class nop_command_mode extends uart_base_test;
244
 
245
    seq_3p1   seq1;
246
    seq_3p2   seq2;
247
    seq_3p3   seq3;
248
    seq_4p1   seq4;
249
    seq_4p2   seq5;
250
    seq_4p3   seq6;
251 2 HanySalah
 
252 3 HanySalah
    `uvm_component_utils(nop_command_mode)
253 2 HanySalah
 
254 3 HanySalah
    function new (string name,uvm_component parent);
255
      super.new(name,parent);
256
    endfunction:new
257 2 HanySalah
 
258 3 HanySalah
    function void build_phase (uvm_phase phase);
259
      super.build_phase(phase);
260
      seq1  = seq_3p1::type_id::create("seq1");
261
      seq2  = seq_3p2::type_id::create("seq2");
262
      seq3  = seq_3p3::type_id::create("seq3");
263
      seq4  = seq_4p1::type_id::create("seq4");
264
      seq5  = seq_4p2::type_id::create("seq5");
265
      seq6  = seq_4p3::type_id::create("seq6");
266
    endfunction:build_phase
267 2 HanySalah
 
268 3 HanySalah
    task run_phase(uvm_phase phase);
269
      super.run_phase(phase);
270
      phase.raise_objection(this);
271
      seq1.start(env.agent._seq,null);
272
      seq2.start(env.agent._seq,null);
273
      seq3.start(env.agent._seq,null);
274
      seq4.start(env.agent._seq,null);
275
      seq5.start(env.agent._seq,null);
276
      seq6.start(env.agent._seq,null);
277
      phase.drop_objection(this);
278
    endtask:run_phase
279
  endclass:nop_command_mode
280 2 HanySalah
 
281
 
282 3 HanySalah
  //  This test apply ten successive tests of UART write request using binary communication mode.
283
  //  Refer to test plan section in the testbench specifications document for more details.
284
  class write_command_mode extends uart_base_test;
285
 
286
    seq_5p1   seq1;
287
    seq_5p2   seq2;
288
    seq_5p3   seq3;
289
    seq_5p4   seq4;
290
    seq_5p5   seq5;
291
    seq_5p6   seq6;
292
    seq_5p7   seq7;
293
    seq_5p8   seq8;
294
    seq_5p9   seq9;
295
    seq_5p10  seq10;
296 2 HanySalah
 
297 3 HanySalah
    `uvm_component_utils(write_command_mode)
298 2 HanySalah
 
299 3 HanySalah
    function new (string name,uvm_component parent);
300
      super.new(name,parent);
301
    endfunction:new
302 2 HanySalah
 
303 3 HanySalah
    function void build_phase (uvm_phase phase);
304
      super.build_phase(phase);
305
      seq1  = seq_5p1::type_id::create("seq1");
306
      seq2  = seq_5p2::type_id::create("seq2");
307
      seq3  = seq_5p3::type_id::create("seq3");
308
      seq4  = seq_5p4::type_id::create("seq4");
309
      seq5  = seq_5p5::type_id::create("seq5");
310
      seq6  = seq_5p6::type_id::create("seq6");
311
      seq7  = seq_5p7::type_id::create("seq7");
312
      seq8  = seq_5p8::type_id::create("seq8");
313
      seq9  = seq_5p9::type_id::create("seq9");
314
      seq10 = seq_5p10::type_id::create("seq10");
315
    endfunction:build_phase
316 2 HanySalah
 
317 3 HanySalah
    task run_phase (uvm_phase phase);
318
      super.run_phase(phase);
319
      phase.raise_objection(this);
320
      uvm_test_done.set_drain_time(this,5000);
321
      //seq1.start(env.agent._seq,null);
322
      seq2.start(env.agent._seq,null);
323
      seq3.start(env.agent._seq,null);
324
      seq4.start(env.agent._seq,null);
325
      seq5.start(env.agent._seq,null);
326
      seq6.start(env.agent._seq,null);
327
      seq7.start(env.agent._seq,null);
328
      seq8.start(env.agent._seq,null);
329
      seq9.start(env.agent._seq,null);
330
      seq10.start(env.agent._seq,null);
331
      phase.drop_objection(this);
332
    endtask:run_phase
333
  endclass: write_command_mode
334 2 HanySalah
 
335
 
336 3 HanySalah
  //  This test apply ten successive tests of UART read request using binary communication mode.
337
  //  Refer to test plan section in the testbench specifications document for more details.
338
  class read_command_mode extends uart_base_test;
339
 
340
    seq_6p1   seq1;
341
    seq_6p2   seq2;
342
    seq_6p3   seq3;
343
    seq_6p4   seq4;
344
    seq_6p5   seq5;
345
    seq_6p6   seq6;
346
    seq_6p7   seq7;
347
    seq_6p8   seq8;
348
    seq_6p9   seq9;
349
    seq_6p10  seq10;
350 2 HanySalah
 
351 3 HanySalah
    `uvm_component_utils(read_command_mode)
352 2 HanySalah
 
353 3 HanySalah
    function new (string name,uvm_component parent);
354
      super.new(name,parent);
355
      seq1  = seq_6p1::type_id::create("seq1");
356
      seq2  = seq_6p2::type_id::create("seq2");
357
      seq3  = seq_6p3::type_id::create("seq3");
358
      seq4  = seq_6p4::type_id::create("seq4");
359
      seq5  = seq_6p5::type_id::create("seq5");
360
      seq6  = seq_6p6::type_id::create("seq6");
361
      seq7  = seq_6p7::type_id::create("seq7");
362
      seq8  = seq_6p8::type_id::create("seq8");
363
      seq9  = seq_6p9::type_id::create("seq9");
364
      seq10 = seq_6p10::type_id::create("seq10");
365
    endfunction:new
366 2 HanySalah
 
367 3 HanySalah
    function void build_phase (uvm_phase phase);
368
      super.build_phase(phase);
369
 
370
    endfunction:build_phase
371
 
372
    task run_phase (uvm_phase phase);
373
      super.run_phase(phase);
374
      phase.raise_objection(this);
375
      //seq1.start(env.agent._seq,null);
376
      seq2.start(env.agent._seq,null);
377
      seq3.start(env.agent._seq,null);
378
      seq4.start(env.agent._seq,null);
379
      seq5.start(env.agent._seq,null);
380
      seq6.start(env.agent._seq,null);
381
      seq7.start(env.agent._seq,null);
382
      seq8.start(env.agent._seq,null);
383
      seq9.start(env.agent._seq,null);
384
      seq10.start(env.agent._seq,null);
385
      phase.drop_objection(this);
386
    endtask:run_phase
387
  endclass:read_command_mode
388
 
389
//-------------------------------------------------------------------------------------------------
390
//
391
//                        COMBINED COMMAND TESTS
392
//
393
//-------------------------------------------------------------------------------------------------
394
 
395
  // this test randomly apply series of 100 text mode commands. They would be either read or write
396
  // sequences described in text mode tests in the testbench specifications document.
397
  class text_mode_test extends uart_base_test;
398
 
399
    rand int unsigned command_number;
400
 
401
    seq_1p1   seq1;
402
    seq_1p2   seq2;
403
    seq_1p3   seq3;
404
    seq_1p4   seq4;
405
    seq_1p5   seq5;
406
    seq_1p6   seq6;
407
    seq_1p7   seq7;
408
    seq_1p8   seq8;
409
    seq_1p9   seq9;
410
    seq_1p10  seq10;
411
    seq_1p11  seq11;
412
    seq_1p12  seq12;
413
    seq_1p13  seq13;
414
 
415
 
416
    seq_2p1   seq14;
417
    seq_2p2   seq15;
418
    seq_2p3   seq16;
419
    seq_2p4   seq17;
420
    seq_2p5   seq18;
421
    seq_2p6   seq19;
422
    seq_2p7   seq20;
423
    seq_2p8   seq21;
424
    seq_2p9   seq22;
425
    seq_2p10  seq23;
426
    seq_2p11  seq24;
427
    seq_2p12  seq25;
428
    seq_2p13  seq26;
429
 
430
    `uvm_component_utils(text_mode_test)
431
 
432
    constraint limit {
433
        command_number inside {[1:26]};
434
    }
435
 
436
    function new (string name , uvm_component parent);
437
      super.new(name,parent);
438
    endfunction:new
439
 
440
    function void build_phase (uvm_phase phase);
441
      super.build_phase(phase);
442
      seq1  = seq_1p1::type_id::create("seq1");
443
      seq2  = seq_1p2::type_id::create("seq2");
444
      seq3  = seq_1p3::type_id::create("seq3");
445
      seq4  = seq_1p4::type_id::create("seq4");
446
      seq5  = seq_1p5::type_id::create("seq5");
447
      seq6  = seq_1p6::type_id::create("seq6");
448
      seq7  = seq_1p7::type_id::create("seq7");
449
      seq8  = seq_1p8::type_id::create("seq8");
450
      seq9  = seq_1p9::type_id::create("seq9");
451
      seq10 = seq_1p10::type_id::create("seq10");
452
      seq11 = seq_1p11::type_id::create("seq11");
453
      seq12 = seq_1p12::type_id::create("seq12");
454
      seq13 = seq_1p13::type_id::create("seq13");
455
      seq14 = seq_2p1::type_id::create("seq14");
456
      seq15 = seq_2p2::type_id::create("seq15");
457
      seq16 = seq_2p3::type_id::create("seq16");
458
      seq17 = seq_2p4::type_id::create("seq17");
459
      seq18 = seq_2p5::type_id::create("seq18");
460
      seq19 = seq_2p6::type_id::create("seq19");
461
      seq20 = seq_2p7::type_id::create("seq20");
462
      seq21 = seq_2p8::type_id::create("seq21");
463
      seq22 = seq_2p9::type_id::create("seq22");
464
      seq23 = seq_2p10::type_id::create("seq23");
465
      seq24 = seq_2p11::type_id::create("seq24");
466
      seq25 = seq_2p12::type_id::create("seq25");
467
      seq26 = seq_2p13::type_id::create("seq26");
468
    endfunction:build_phase
469
 
470
    task run_phase (uvm_phase phase);
471
      super.run_phase(phase);
472
      phase.raise_objection(this);
473
      repeat (100)
474
        begin
475
        randomize();
476
        case (command_number)
477
          1:
478
            begin
479
            seq1.start(env.agent._seq,null);
480
            end
481
          2:
482
            begin
483
            seq2.start(env.agent._seq,null);
484
            end
485
          3:
486
            begin
487
            seq3.start(env.agent._seq,null);
488
            end
489
          4:
490
            begin
491
            seq4.start(env.agent._seq,null);
492
            end
493
          5:
494
            begin
495
            seq5.start(env.agent._seq,null);
496
            end
497
          6:
498
            begin
499
            seq6.start(env.agent._seq,null);
500
            end
501
          7:
502
            begin
503
            seq7.start(env.agent._seq,null);
504
            end
505
          8:
506
            begin
507
            seq8.start(env.agent._seq,null);
508
            end
509
          9:
510
            begin
511
            seq9.start(env.agent._seq,null);
512
            end
513
          10:
514
            begin
515
            seq10.start(env.agent._seq,null);
516
            end
517
          11:
518
            begin
519
            seq11.start(env.agent._seq,null);
520
            end
521
          12:
522
            begin
523
            seq12.start(env.agent._seq,null);
524
            end
525
          13:
526
            begin
527
            seq13.start(env.agent._seq,null);
528
            end
529
          14:
530
            begin
531
            seq14.start(env.agent._seq,null);
532
            end
533
          15:
534
            begin
535
            seq15.start(env.agent._seq,null);
536
            end
537
          16:
538
            begin
539
            seq16.start(env.agent._seq,null);
540
            end
541
          17:
542
            begin
543
            seq17.start(env.agent._seq,null);
544
            end
545
          18:
546
            begin
547
            seq18.start(env.agent._seq,null);
548
            end
549
          19:
550
            begin
551
            seq19.start(env.agent._seq,null);
552
            end
553
          20:
554
            begin
555
            seq20.start(env.agent._seq,null);
556
            end
557
          21:
558
            begin
559
            seq21.start(env.agent._seq,null);
560
            end
561
          22:
562
            begin
563
            seq22.start(env.agent._seq,null);
564
            end
565
          23:
566
            begin
567
            seq23.start(env.agent._seq,null);
568
            end
569
          24:
570
            begin
571
            seq24.start(env.agent._seq,null);
572
            end
573
          25:
574
            begin
575
            seq25.start(env.agent._seq,null);
576
            end
577
          26:
578
            begin
579
            seq26.start(env.agent._seq,null);
580
            end
581
          default:
582
            begin
583
            `uvm_fatal("OUT OF RANGE","Command Number is Out of Range")
584
            end
585
        endcase
586
        end
587
        phase.drop_objection(this);
588
    endtask:run_phase
589
  endclass:text_mode_test

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