OpenCores
URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [uvm_src/] [reg/] [uvm_reg_adapter.svh] - Blame information for rev 16

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 HanySalah
//
2
// -------------------------------------------------------------
3
//    Copyright 2004-2009 Synopsys, Inc.
4
//    Copyright 2010 Mentor Graphics Corporation
5
//    All Rights Reserved Worldwide
6
//
7
//    Licensed under the Apache License, Version 2.0 (the
8
//    "License"); you may not use this file except in
9
//    compliance with the License.  You may obtain a copy of
10
//    the License at
11
//
12
//        http://www.apache.org/licenses/LICENSE-2.0
13
//
14
//    Unless required by applicable law or agreed to in
15
//    writing, software distributed under the License is
16
//    distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
17
//    CONDITIONS OF ANY KIND, either express or implied.  See
18
//    the License for the specific language governing
19
//    permissions and limitations under the License.
20
// -------------------------------------------------------------
21
//
22
 
23
//------------------------------------------------------------------------------
24
// Title: Classes for Adapting Between Register and Bus Operations
25
//
26
// This section defines classes used to convert transaction streams between
27
// generic register address/data reads and writes and physical bus accesses.
28
//------------------------------------------------------------------------------
29
 
30
 
31
//------------------------------------------------------------------------------
32
//
33
// Class: uvm_reg_adapter
34
//
35
// This class defines an interface for converting between 
36
// and a specific bus transaction.
37
//------------------------------------------------------------------------------
38
 
39
virtual class uvm_reg_adapter extends uvm_object;
40
 
41
  // Function: new
42
  //
43
  // Create a new instance of this type, giving it the optional ~name~.
44
 
45
  function new(string name="");
46
    super.new(name);
47
  endfunction
48
 
49
 
50
  // Variable: supports_byte_enable
51
  //
52
  // Set this bit in extensions of this class if the bus protocol supports
53
  // byte enables.
54
 
55
  bit supports_byte_enable;
56
 
57
 
58
  // Variable: provides_responses
59
  //
60
  // Set this bit in extensions of this class if the bus driver provides
61
  // separate response items.
62
 
63
  bit provides_responses;
64
 
65
 
66
  // Variable: parent_sequence
67
  //
68
  // Set this member in extensions of this class if the bus driver requires
69
  // bus items be executed via a particular sequence base type. The sequence
70
  // assigned to this member must implement do_clone().
71
 
72
  uvm_sequence_base parent_sequence;
73
 
74
 
75
  // Function: reg2bus
76
  //
77
  // Extensions of this class ~must~ implement this method to convert the specified
78
  //  to a corresponding  subtype that defines the bus
79
  // transaction.
80
  //
81
  // The method must allocate a new bus-specific ,
82
  // assign its members from
83
  // the corresponding members from the given generic ~rw~ bus operation, then
84
  // return it.
85
 
86
  pure virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
87
 
88
 
89
  // Function: bus2reg
90
  //
91
  // Extensions of this class ~must~ implement this method to copy members
92
  // of the given bus-specific ~bus_item~ to corresponding members of the provided
93
  // ~bus_rw~ instance. Unlike , the resulting transaction
94
  // is not allocated from scratch. This is to accommodate applications
95
  // where the bus response must be returned in the original request.
96
 
97
  pure virtual function void bus2reg(uvm_sequence_item bus_item,
98
                                     ref uvm_reg_bus_op rw);
99
 
100
 
101
  local uvm_reg_item m_item;
102
 
103
  // function: get_item
104
  //
105
  // Returns the bus-independent read/write information that corresponds to
106
  // the generic bus transaction currently translated to a bus-specific
107
  // transaction.
108
  // This function returns a value reference only when called in the
109
  //  method.
110
  // It returns ~null~ at all other times.
111
  // The content of the return  instance must not be modified
112
  // and used strictly to obtain additional information about the operation.
113
  virtual function uvm_reg_item get_item();
114
    return m_item;
115
  endfunction
116
 
117
  virtual function void m_set_item(uvm_reg_item item);
118
    m_item = item;
119
  endfunction
120
endclass
121
 
122
 
123
//------------------------------------------------------------------------------
124
// Group: Example
125
//
126
// The following example illustrates how to implement a RegModel-BUS adapter class
127
// for the APB bus protocol.
128
//
129
//|class rreg2apb_adapter extends uvm_reg_adapter;
130
//|  `uvm_object_utils(reg2apb_adapter)
131
//|
132
//|  function new(string name="reg2apb_adapter");
133
//|    super.new(name);
134
//|
135
//|  endfunction
136
//|
137
//|  virtual function uvm_sequence_item reg2bus(uvm_reg_bus_op rw);
138
//|    apb_item apb = apb_item::type_id::create("apb_item");
139
//|    apb.op   = (rw.kind == UVM_READ) ? apb::READ : apb::WRITE;
140
//|    apb.addr = rw.addr;
141
//|    apb.data = rw.data;
142
//|    return apb;
143
//|  endfunction
144
//|
145
//|  virtual function void bus2reg(uvm_sequencer_item bus_item,
146
//|                                uvm_reg_bus_op rw);
147
//|    apb_item apb;
148
//|    if (!$cast(apb,bus_item)) begin
149
//|      `uvm_fatal("CONVERT_APB2REG","Bus item is not of type apb_item")
150
//|    end
151
//|    rw.kind  = apb.op==apb::READ ? UVM_READ : UVM_WRITE;
152
//|    rw.addr = apb.addr;
153
//|    rw.data = apb.data;
154
//|    rw.status = UVM_IS_OK;
155
//|  endfunction
156
//|
157
//|endclass
158
//
159
//------------------------------------------------------------------------------
160
 
161
 
162
//------------------------------------------------------------------------------
163
//
164
// Class: uvm_reg_tlm_adapter
165
//
166
// For converting between  and  items.
167
//
168
//------------------------------------------------------------------------------
169
 
170
class uvm_reg_tlm_adapter extends uvm_reg_adapter;
171
 
172
  `uvm_object_utils(uvm_reg_tlm_adapter)
173
 
174
  function new(string name = "uvm_reg_tlm_adapter");
175
    super.new(name);
176
  endfunction
177
 
178
  // Function: reg2bus
179
  //
180
  // Converts a  struct to a  item.
181
 
182
  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
183
 
184
     uvm_tlm_gp gp = uvm_tlm_gp::type_id::create("tlm_gp",, this.get_full_name());
185
     int nbytes = (rw.n_bits-1)/8+1;
186
     uvm_reg_addr_t addr=rw.addr;
187
 
188
     if (rw.kind == UVM_WRITE)
189
        gp.set_command(UVM_TLM_WRITE_COMMAND);
190
     else
191
        gp.set_command(UVM_TLM_READ_COMMAND);
192
 
193
     gp.set_address(addr);
194
 
195
     gp.m_byte_enable = new [nbytes];
196
     gp.m_byte_enable_length = nbytes;
197
 
198
     gp.set_streaming_width (nbytes);
199
 
200
     gp.m_data = new [gp.get_streaming_width()];
201
     gp.m_length = nbytes;
202
 
203
     for (int i = 0; i < nbytes; i++) begin
204
        gp.m_data[i] = rw.data[i*8+:8];
205
        gp.m_byte_enable[i] = (i > nbytes) ? 8'h00 : (rw.byte_en[i] ? 8'hFF : 8'h00);
206
     end
207
 
208
     return gp;
209
 
210
  endfunction
211
 
212
 
213
  // Function: bus2reg
214
  //
215
  // Converts a  item to a .
216
  // into the provided ~rw~ transaction.
217
  //
218
  virtual function void bus2reg(uvm_sequence_item bus_item,
219
                                ref uvm_reg_bus_op rw);
220
 
221
    uvm_tlm_gp gp;
222
    int nbytes;
223
 
224
    if (bus_item == null)
225
     `uvm_fatal("REG/NULL_ITEM","bus2reg: bus_item argument is null")
226
 
227
    if (!$cast(gp,bus_item)) begin
228
      `uvm_error("WRONG_TYPE","Provided bus_item is not of type uvm_tlm_gp")
229
      return;
230
    end
231
 
232
    if (gp.get_command() == UVM_TLM_WRITE_COMMAND)
233
      rw.kind = UVM_WRITE;
234
    else
235
      rw.kind = UVM_READ;
236
 
237
    rw.addr = gp.get_address();
238
 
239
    rw.byte_en = 0;
240
    foreach (gp.m_byte_enable[i])
241
      rw.byte_en[i] = gp.m_byte_enable[i];
242
 
243
    rw.data = 0;
244
    foreach (gp.m_data[i])
245
      rw.data[i*8+:8] = gp.m_data[i];
246
 
247
    rw.status = (gp.is_response_ok()) ? UVM_IS_OK : UVM_NOT_OK;
248
 
249
 
250
  endfunction
251
 
252
endclass
253
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.