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// ============================================================================
//        __
//   \\__/ o\    (C) 2004-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//       ||
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
//    contributors may be used to endorse or promote products derived from
//    this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
//
`define IDLE    0
`define CNT             1
 
//`define UART_NO_TX_FIFO       1'b1
 
module uart6551Tx(rst, clk, cyc, cs, wr, din, ack,
        fifoEnable, fifoClear, txBreak,
        frameSize, wordLength, parityCtrl, baud16x_ce,
        cts, clear, txd, full, empty, qcnt);
 
input rst;
input clk;
input cyc;                      // bus cycle valid
input cs;                       // core select
input wr;                       // write transmitter
input [7:0] din;                // fifo data in
output ack;
 
input fifoEnable;
input fifoClear;
input txBreak;
input [7:0] frameSize;
input [3:0] wordLength;
input [2:0] parityCtrl;
input baud16x_ce;       // baud rate clock enable
input cts;                      // clear to send
input clear;            // clear transmitter
output reg txd;         // external serial output
output full;            // fifo is full
output empty;           // fifo is empty
output [3:0] qcnt;      // number of characters queued
 
reg [7:0] t1;
reg [11:0] t2;
reg [11:0] tx_data;     // transmit data working reg (raw)
reg state;                      // state machine state
reg [7:0] cnt;          // baud clock counter
reg rd;
reg p1, p2;                     // parity bit
 
assign ack = cyc & cs;
edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & wr), .pe(awr), .ne(), .ee());
 
`ifdef UART_NO_TX_FIFO
reg [7:0] fdo2;
reg empty;
 
always @(posedge clk)
        if (awr) fdo2 <= {3'd0,din};
 
always @(posedge clk)
        begin
                if (awr) empty <= 0;
                else if (rd) empty <= 1;
        end
 
assign full = ~empty;
wire [7:0] fdo = fdo2;
`else
reg [7:0] fdo2;
always @(posedge clk)
        if (awr) fdo2 <= {3'd0,din};
// generate an empty signal for when the fifo is disabled
reg fempty2;
always @(posedge clk)
        if (rst)
                fempty2 <= 1;
        else begin
                if (awr) fempty2 <= 0;
                else if (rd) fempty2 <= 1;
        end
 
 
wire [7:0] fdo1;                // fifo data output
wire rdf = fifoEnable ? rd : awr;
wire fempty;
wire ffull;
uart6551Fifo #(.WID(8)) fifo0
(
  .clk(clk),
  .rst(rst|clear|fifoClear),
  .din(din),
  .wr(awr),
  .rd(rdf),
  .dout(fdo1),
  .full(ffull),
  .empty(fempty),
  .ctr(qcnt)
);
assign empty = fifoEnable ? fempty : fempty2;
assign full = fifoEnable ? ffull : ~fempty2;
wire [7:0] fdo = fifoEnable ? fdo1 : fdo2;
`endif
 
// mask transmit data for word length
// this mask is needed for proper parity generation
integer n;
reg [7:0] mask;
always @*
        for (n = 0; n < 8; n = n + 1)
                mask[n] = n < wordLength ? 1'b1 : 1'b0;
 
always @*
if (txBreak)
        t1 <= 0;
else
        t1 <= fdo & mask;
 
 
// compute parity bit
always @*
begin
        case (parityCtrl)
        3'b001: p1 <= ~^t1;// odd parity
        3'b011: p1 <= ^t1;      // even parity
        3'b101: p1 <= 1;        // mark bit
        3'b111: p1 <= 0;        // space bit
        default: p1 <= 1;       // stop bit when no parity
        endcase
end
 
/*
Could pipeline this, but then watch out for empty signal control
always @(posedge clk)
        if (ce) t2 <= t1;
 
always @(posedge clk)
        if (ce) p2 <= p1;
*/
// Insert start, parity bit and stop
always @*
case(wordLength)
4'd5:   t2 <= {5'b11111,p1,t1[4:0],1'b0};
4'd6:   t2 <= {4'b1111,p1,t1[5:0],1'b0};
4'd7:   t2 <= {3'b111,p1,t1[6:0],1'b0};
default:        t2 <= {2'b11,p1,t1[7:0],1'b0};
endcase
 
always @(posedge clk)
if (rst)
        state <= `IDLE;
else begin
        if (clear)
                state <= `IDLE;
        if (baud16x_ce) begin
                case(state)
                `IDLE:
                        if ((!empty && cts)||txBreak)
                                state <= `CNT;
                `CNT:
                        if (cnt==frameSize)
                                state <= `IDLE;
                endcase
        end
end
 
always @(posedge clk)
if (rst)
        cnt <= 8'h00;
else begin
        if (clear)
                cnt <= 8'h00;
        if (baud16x_ce) begin
                case(state)
                `IDLE:
                        cnt <= 8'h00;
                `CNT:
                        cnt <= cnt + 8'd1;
                endcase
        end
end
 
always @(posedge clk)
if (rst)
        rd <= 0;
else begin
        rd <= 0;
        if (clear)
                rd <= 0;
        if (baud16x_ce) begin
                case(state)
                `IDLE:
                        if ((!empty && cts)||txBreak)
                                rd <= 1;
                endcase
        end
end
 
always @(posedge clk)
if (rst)
        tx_data <= 12'hFFF;
else begin
        if (baud16x_ce) begin
                case(state)
                `IDLE:
                        if ((!empty && cts)||txBreak)
                                tx_data <= t2;
                `CNT:
                        // Shift the data out. LSB first.
                        if (cnt[3:0]==4'hF)
                                tx_data <= {1'b1,tx_data[11:1]};
                endcase
        end
end
 
always @(posedge clk)
if (rst)
        txd <= 1'b1;
else
        txd <= tx_data[0];
 
endmodule

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// __`
3	8	robfinch	`// \\__/ o\ (C) 2004-2022 Robert Finch, Waterloo`
4	2	robfinch	`// \ __ / All rights reserved.`
5			`// \/_// robfinch@finitron.ca`
6			`// \|\|`
7			`//`
8			`//`
9	8	robfinch	`// BSD 3-Clause License`
10			`// Redistribution and use in source and binary forms, with or without`
11			`// modification, are permitted provided that the following conditions are met:`
12	2	robfinch	`//`
13	8	robfinch	`// 1. Redistributions of source code must retain the above copyright notice, this`
14			`// list of conditions and the following disclaimer.`
15			`//`
16			`// 2. Redistributions in binary form must reproduce the above copyright notice,`
17			`// this list of conditions and the following disclaimer in the documentation`
18			`// and/or other materials provided with the distribution.`
19			`//`
20			`// 3. Neither the name of the copyright holder nor the names of its`
21			`// contributors may be used to endorse or promote products derived from`
22			`// this software without specific prior written permission.`
23			`//`
24			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
25			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
26			`// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
27			`// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE`
28			`// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
29			`// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
30			`// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
31			`// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,`
32			`// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`
33			`// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
34			`//`
35	2	robfinch	`// ============================================================================`
36			`//`
37			`define IDLE 0
38			`define CNT 1
39
40	3	robfinch	//`define UART_NO_TX_FIFO 1'b1
41
42	2	robfinch	`module uart6551Tx(rst, clk, cyc, cs, wr, din, ack,`
43			`fifoEnable, fifoClear, txBreak,`
44			`frameSize, wordLength, parityCtrl, baud16x_ce,`
45			`cts, clear, txd, full, empty, qcnt);`
46
47			`input rst;`
48			`input clk;`
49			`input cyc; // bus cycle valid`
50			`input cs; // core select`
51			`input wr; // write transmitter`
52			`input [7:0] din; // fifo data in`
53			`output ack;`
54
55			`input fifoEnable;`
56			`input fifoClear;`
57			`input txBreak;`
58			`input [7:0] frameSize;`
59			`input [3:0] wordLength;`
60			`input [2:0] parityCtrl;`
61			`input baud16x_ce; // baud rate clock enable`
62			`input cts; // clear to send`
63			`input clear; // clear transmitter`
64			`output reg txd; // external serial output`
65			`output full; // fifo is full`
66			`output empty; // fifo is empty`
67			`output [3:0] qcnt; // number of characters queued`
68
69			`reg [7:0] t1;`
70			`reg [11:0] t2;`
71			`reg [11:0] tx_data; // transmit data working reg (raw)`
72			`reg state; // state machine state`
73			`reg [7:0] cnt; // baud clock counter`
74			`reg rd;`
75			`reg p1, p2; // parity bit`
76
77			`assign ack = cyc & cs;`
78			`edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & wr), .pe(awr), .ne(), .ee());`
79
80			`ifdef UART_NO_TX_FIFO
81	3	robfinch	`reg [7:0] fdo2;`
82	2	robfinch	`reg empty;`
83
84			`always @(posedge clk)`
85	3	robfinch	`if (awr) fdo2 <= {3'd0,din};`
86	2	robfinch
87			`always @(posedge clk)`
88			`begin`
89			`if (awr) empty <= 0;`
90			`else if (rd) empty <= 1;`
91			`end`
92
93			`assign full = ~empty;`
94	3	robfinch	`wire [7:0] fdo = fdo2;`
95	2	robfinch	`else
96	3	robfinch	`reg [7:0] fdo2;`
97			`always @(posedge clk)`
98			`if (awr) fdo2 <= {3'd0,din};`
99	2	robfinch	`// generate an empty signal for when the fifo is disabled`
100			`reg fempty2;`
101			`always @(posedge clk)`
102			`if (rst)`
103			`fempty2 <= 1;`
104			`else begin`
105			`if (awr) fempty2 <= 0;`
106			`else if (rd) fempty2 <= 1;`
107			`end`
108
109
110	3	robfinch	`wire [7:0] fdo1; // fifo data output`
111	2	robfinch	`wire rdf = fifoEnable ? rd : awr;`
112			`wire fempty;`
113			`wire ffull;`
114			`uart6551Fifo #(.WID(8)) fifo0`
115			`(`
116			`.clk(clk),`
117			`.rst(rst\|clear\|fifoClear),`
118			`.din(din),`
119			`.wr(awr),`
120			`.rd(rdf),`
121	3	robfinch	`.dout(fdo1),`
122	2	robfinch	`.full(ffull),`
123			`.empty(fempty),`
124			`.ctr(qcnt)`
125			`);`
126			`assign empty = fifoEnable ? fempty : fempty2;`
127			`assign full = fifoEnable ? ffull : ~fempty2;`
128	3	robfinch	`wire [7:0] fdo = fifoEnable ? fdo1 : fdo2;`
129	2	robfinch	`endif
130
131			`// mask transmit data for word length`
132			`// this mask is needed for proper parity generation`
133			`integer n;`
134			`reg [7:0] mask;`
135			`always @*`
136			`for (n = 0; n < 8; n = n + 1)`
137			`mask[n] = n < wordLength ? 1'b1 : 1'b0;`
138
139			`always @*`
140			`if (txBreak)`
141			`t1 <= 0;`
142			`else`
143			`t1 <= fdo & mask;`
144
145
146			`// compute parity bit`
147			`always @*`
148			`begin`
149			`case (parityCtrl)`
150			`3'b001: p1 <= ~^t1;// odd parity`
151			`3'b011: p1 <= ^t1; // even parity`
152			`3'b101: p1 <= 1; // mark bit`
153			`3'b111: p1 <= 0; // space bit`
154			`default: p1 <= 1; // stop bit when no parity`
155			`endcase`
156			`end`
157
158			`/*`
159			`Could pipeline this, but then watch out for empty signal control`
160			`always @(posedge clk)`
161			`if (ce) t2 <= t1;`
162
163			`always @(posedge clk)`
164			`if (ce) p2 <= p1;`
165			`*/`
166			`// Insert start, parity bit and stop`
167			`always @*`
168			`case(wordLength)`
169			`4'd5: t2 <= {5'b11111,p1,t1[4:0],1'b0};`
170			`4'd6: t2 <= {4'b1111,p1,t1[5:0],1'b0};`
171			`4'd7: t2 <= {3'b111,p1,t1[6:0],1'b0};`
172			`default: t2 <= {2'b11,p1,t1[7:0],1'b0};`
173			`endcase`
174
175			`always @(posedge clk)`
176			`if (rst)`
177			state <= `IDLE;
178			`else begin`
179			`if (clear)`
180			state <= `IDLE;
181			`if (baud16x_ce) begin`
182			`case(state)`
183			`IDLE:
184			`if ((!empty && cts)\|\|txBreak)`
185			state <= `CNT;
186			`CNT:
187			`if (cnt==frameSize)`
188			state <= `IDLE;
189			`endcase`
190			`end`
191			`end`
192
193			`always @(posedge clk)`
194			`if (rst)`
195			`cnt <= 8'h00;`
196			`else begin`
197			`if (clear)`
198			`cnt <= 8'h00;`
199			`if (baud16x_ce) begin`
200			`case(state)`
201			`IDLE:
202			`cnt <= 8'h00;`
203			`CNT:
204			`cnt <= cnt + 8'd1;`
205			`endcase`
206			`end`
207			`end`
208
209			`always @(posedge clk)`
210			`if (rst)`
211			`rd <= 0;`
212			`else begin`
213			`rd <= 0;`
214			`if (clear)`
215			`rd <= 0;`
216			`if (baud16x_ce) begin`
217			`case(state)`
218			`IDLE:
219			`if ((!empty && cts)\|\|txBreak)`
220			`rd <= 1;`
221			`endcase`
222			`end`
223			`end`
224
225			`always @(posedge clk)`
226			`if (rst)`
227			`tx_data <= 12'hFFF;`
228			`else begin`
229			`if (baud16x_ce) begin`
230			`case(state)`
231			`IDLE:
232			`if ((!empty && cts)\|\|txBreak)`
233			`tx_data <= t2;`
234			`CNT:
235			`// Shift the data out. LSB first.`
236			`if (cnt[3:0]==4'hF)`
237			`tx_data <= {1'b1,tx_data[11:1]};`
238			`endcase`
239			`end`
240			`end`
241
242			`always @(posedge clk)`
243			`if (rst)`
244			`txd <= 1'b1;`
245			`else`
246			`txd <= tx_data[0];`
247
248			`endmodule`

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[/] [uart6551/] [trunk/] [trunk/] [rtl/] [uart6551Tx.sv] - Blame information for rev 8