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leonardoar |
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave
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| 2 |
21 |
leonardoar |
ISim O.87xd (signature 0x8ddf5b5d)
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| 3 |
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Number of CPUs detected in this system: 4
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| 4 |
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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| 5 |
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Determining compilation order of HDL files
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| 6 |
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
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| 7 |
22 |
leonardoar |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
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| 8 |
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
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| 9 |
21 |
leonardoar |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work
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| 10 |
22 |
leonardoar |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work
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| 11 |
21 |
leonardoar |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work
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| 12 |
22 |
leonardoar |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
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| 13 |
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WARNING:HDLCompiler:946 - "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression
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| 14 |
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
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| 15 |
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
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| 16 |
21 |
leonardoar |
Starting static elaboration
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| 17 |
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Completed static elaboration
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| 18 |
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leonardoar |
Fuse Memory Usage: 37476 KB
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| 19 |
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leonardoar |
Fuse CPU Usage: 1100 ms
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| 20 |
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Compiling package standard
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| 21 |
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Compiling package std_logic_1164
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| 22 |
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Compiling package std_logic_arith
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| 23 |
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Compiling package std_logic_unsigned
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| 24 |
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Compiling package pkgdefinitions
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| 25 |
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Compiling architecture behavioral of entity divisor [divisor_default]
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| 26 |
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Compiling architecture behavioral of entity uart_control [uart_control_default]
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| 27 |
22 |
leonardoar |
Compiling package numeric_std
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| 28 |
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Compiling architecture behavioral of entity baud_generator [baud_generator_default]
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| 29 |
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Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
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| 30 |
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Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
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| 31 |
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Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
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| 32 |
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Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
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| 33 |
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Compiling architecture behavior of entity testuart_wishbone_slave
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| 34 |
21 |
leonardoar |
Time Resolution for simulation is 1ps.
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| 35 |
22 |
leonardoar |
Compiled 21 VHDL Units
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| 36 |
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Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
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| 37 |
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Fuse Memory Usage: 91188 KB
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| 38 |
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Fuse CPU Usage: 1280 ms
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| 39 |
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GCC CPU Usage: 710 ms
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