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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.log] - Blame information for rev 23

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Line No. Rev Author Line
1 21 leonardoar 
ISim log file
2 22 leonardoar 
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
3 21 leonardoar 
ISim O.87xd (signature 0x8ddf5b5d)
4 
WARNING: A WEBPACK license was found.
5 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
6 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
7 
This is a Lite version of ISim.
8 
Time resolution is 1 ps
9 
# onerror resume
10 
# wave add /
11 
# run 1000 ms
12 
Simulator is doing circuit initialization process.
13 
Finished circuit initialization process.
14 22 leonardoar 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
15 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
16 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
17 21 leonardoar 
 
18 
** Failure:NONE. End of simulation.
19 
User(VHDL) Code Called Simulation Stop
20 22 leonardoar 
In process testUart_wishbone_slave.vhd:stim_proc
21 21 leonardoar 
 
22 
INFO: Simulator is stopped.
23 23 leonardoar 
ISim O.87xd (signature 0x8ddf5b5d)
24 
WARNING: A WEBPACK license was found.
25 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
26 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
27 
This is a Lite version of ISim.
28 
# run 1000 ms
29 
Simulator is doing circuit initialization process.
30 
Finished circuit initialization process.
31 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
32 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
33 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
34 
 
35 
** Failure:NONE. End of simulation.
36 
User(VHDL) Code Called Simulation Stop
37 
In process testUart_wishbone_slave.vhd:stim_proc
38 
 
39 
INFO: Simulator is stopped.
40 
ISim O.87xd (signature 0x8ddf5b5d)
41 
WARNING: A WEBPACK license was found.
42 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
43 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
44 
This is a Lite version of ISim.
45 
# run 1000 ms
46 
Simulator is doing circuit initialization process.
47 
Finished circuit initialization process.
48 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
49 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
50 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
51 
 
52 
** Failure:NONE. End of simulation.
53 
User(VHDL) Code Called Simulation Stop
54 
In process testUart_wishbone_slave.vhd:stim_proc
55 
 
56 
INFO: Simulator is stopped.
57 
ISim O.87xd (signature 0x8ddf5b5d)
58 
WARNING: A WEBPACK license was found.
59 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
60 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
61 
This is a Lite version of ISim.
62 
# run 1000 ms
63 
Simulator is doing circuit initialization process.
64 
Finished circuit initialization process.
65 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
66 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
67 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
68 
 
69 
** Failure:NONE. End of simulation.
70 
User(VHDL) Code Called Simulation Stop
71 
In process testUart_wishbone_slave.vhd:stim_proc
72 
 
73 
INFO: Simulator is stopped.
74 
ISim O.87xd (signature 0x8ddf5b5d)
75 
WARNING: A WEBPACK license was found.
76 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
77 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
78 
This is a Lite version of ISim.
79 
# run 1000 ms
80 
Simulator is doing circuit initialization process.
81 
Finished circuit initialization process.
82 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
83 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
84 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
85 
Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 116
86 
# run all
87 
 
88 
** Failure:NONE. End of simulation.
89 
User(VHDL) Code Called Simulation Stop
90 
In process testUart_wishbone_slave.vhd:stim_proc
91 
 
92 
INFO: Simulator is stopped.
93 
ISim O.87xd (signature 0x8ddf5b5d)
94 
WARNING: A WEBPACK license was found.
95 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
96 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
97 
This is a Lite version of ISim.
98 
# run 1000 ms
99 
Simulator is doing circuit initialization process.
100 
Finished circuit initialization process.
101 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
102 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
103 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
104 
Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 116
105 
# run all
106 
 
107 
** Failure:NONE. End of simulation.
108 
User(VHDL) Code Called Simulation Stop
109 
In process testUart_wishbone_slave.vhd:stim_proc
110 
 
111 
INFO: Simulator is stopped.
112 
ISim O.87xd (signature 0x8ddf5b5d)
113 
WARNING: A WEBPACK license was found.
114 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
115 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
116 
This is a Lite version of ISim.
117 
# run 1000 ms
118 
Simulator is doing circuit initialization process.
119 
Finished circuit initialization process.
120 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
121 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
122 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
123 
 
124 
** Failure:NONE. End of simulation.
125 
User(VHDL) Code Called Simulation Stop
126 
In process testUart_wishbone_slave.vhd:stim_proc
127 
 
128 
INFO: Simulator is stopped.
129 
ISim O.87xd (signature 0x8ddf5b5d)
130 
WARNING: A WEBPACK license was found.
131 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
132 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
133 
This is a Lite version of ISim.
134 
# run 1000 ms
135 
Simulator is doing circuit initialization process.
136 
Finished circuit initialization process.
137 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
138 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
139 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
140 
 
141 
** Failure:NONE. End of simulation.
142 
User(VHDL) Code Called Simulation Stop
143 
In process testUart_wishbone_slave.vhd:stim_proc
144 
 
145 
INFO: Simulator is stopped.
146 
ISim O.87xd (signature 0x8ddf5b5d)
147 
WARNING: A WEBPACK license was found.
148 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
149 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
150 
This is a Lite version of ISim.
151 
# run 1000 ms
152 
Simulator is doing circuit initialization process.
153 
Finished circuit initialization process.
154 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
155 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
156 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
157 
Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 105
158 
ISim O.87xd (signature 0x8ddf5b5d)
159 
WARNING: A WEBPACK license was found.
160 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
161 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
162 
This is a Lite version of ISim.
163 
# run 1000 ms
164 
Simulator is doing circuit initialization process.
165 
Finished circuit initialization process.
166 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 186
167 
ISim O.87xd (signature 0x8ddf5b5d)
168 
WARNING: A WEBPACK license was found.
169 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
170 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
171 
This is a Lite version of ISim.
172 
# run 1000 ms
173 
Simulator is doing circuit initialization process.
174 
Finished circuit initialization process.
175 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
176 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
177 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
178 
Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 104
179 
# run all
180 
 
181 
** Failure:NONE. End of simulation.
182 
User(VHDL) Code Called Simulation Stop
183 
In process testUart_wishbone_slave.vhd:stim_proc
184 
 
185 
INFO: Simulator is stopped.
186 
ISim O.87xd (signature 0x8ddf5b5d)
187 
WARNING: A WEBPACK license was found.
188 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
189 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
190 
This is a Lite version of ISim.
191 
# run 1000 ms
192 
Simulator is doing circuit initialization process.
193 
Finished circuit initialization process.
194 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
195 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
196 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
197 
Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 105
198 
# run all
199 
Stopped at time : 970 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 105
200 
# run all
201 
 
202 
** Failure:NONE. End of simulation.
203 
User(VHDL) Code Called Simulation Stop
204 
In process testUart_wishbone_slave.vhd:stim_proc
205 
 
206 
INFO: Simulator is stopped.
207 
ISim O.87xd (signature 0x8ddf5b5d)
208 
WARNING: A WEBPACK license was found.
209 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
210 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
211 
This is a Lite version of ISim.
212 
# run 1000 ms
213 
Simulator is doing circuit initialization process.
214 
Finished circuit initialization process.
215 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
216 
# run all
217 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
218 
# run all
219 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
220 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
221 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
222 
Stopped at time : 850 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
223 
# run all
224 
Stopped at time : 870 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
225 
# run all
226 
Stopped at time : 890 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
227 
# run all
228 
Stopped at time : 910 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
229 
# run all
230 
Stopped at time : 930 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
231 
# run all
232 
Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
233 
# run all
234 
Stopped at time : 970 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
235 
# run all
236 
Stopped at time : 990 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
237 
# run all
238 
Stopped at time : 1010 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
239 
# run all
240 
Stopped at time : 1030 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
241 
# run all
242 
Stopped at time : 1050 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
243 
ISim O.87xd (signature 0x8ddf5b5d)
244 
WARNING: A WEBPACK license was found.
245 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
246 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
247 
This is a Lite version of ISim.
248 
# run 1000 ms
249 
Simulator is doing circuit initialization process.
250 
Finished circuit initialization process.
251 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
252 
# run all
253 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
254 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
255 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
256 
 
257 
** Failure:NONE. End of simulation.
258 
User(VHDL) Code Called Simulation Stop
259 
In process testUart_wishbone_slave.vhd:stim_proc
260 
 
261 
INFO: Simulator is stopped.
262 
ISim O.87xd (signature 0x8ddf5b5d)
263 
WARNING: A WEBPACK license was found.
264 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
265 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
266 
This is a Lite version of ISim.
267 
# run 1000 ms
268 
Simulator is doing circuit initialization process.
269 
Finished circuit initialization process.
270 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
271 
# run all
272 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
273 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
274 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
275 
Stopped at time : 910 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
276 
# run all
277 
Stopped at time : 990 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
278 
# run all
279 
 
280 
** Failure:NONE. End of simulation.
281 
User(VHDL) Code Called Simulation Stop
282 
In process testUart_wishbone_slave.vhd:stim_proc
283 
 
284 
INFO: Simulator is stopped.
285 
ISim O.87xd (signature 0x8ddf5b5d)
286 
WARNING: A WEBPACK license was found.
287 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
288 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
289 
This is a Lite version of ISim.
290 
# run 1000 ms
291 
Simulator is doing circuit initialization process.
292 
Finished circuit initialization process.
293 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
294 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
295 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
296 
 
297 
** Failure:NONE. End of simulation.
298 
User(VHDL) Code Called Simulation Stop
299 
In process testUart_wishbone_slave.vhd:stim_proc
300 
 
301 
INFO: Simulator is stopped.
302 
ISim O.87xd (signature 0x8ddf5b5d)
303 
WARNING: A WEBPACK license was found.
304 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
305 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
306 
This is a Lite version of ISim.
307 
# run 1000 ms
308 
Simulator is doing circuit initialization process.
309 
Finished circuit initialization process.
310 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
311 
# run all
312 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
313 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
314 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
315 
 
316 
** Failure:NONE. End of simulation.
317 
User(VHDL) Code Called Simulation Stop
318 
In process testUart_wishbone_slave.vhd:stim_proc
319 
 
320 
INFO: Simulator is stopped.
321 
ISim O.87xd (signature 0x8ddf5b5d)
322 
WARNING: A WEBPACK license was found.
323 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
324 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
325 
This is a Lite version of ISim.
326 
# run 1000 ms
327 
Simulator is doing circuit initialization process.
328 
Finished circuit initialization process.
329 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
330 
ISim O.87xd (signature 0x8ddf5b5d)
331 
WARNING: A WEBPACK license was found.
332 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
333 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
334 
This is a Lite version of ISim.
335 
# run 1000 ms
336 
Simulator is doing circuit initialization process.
337 
Stopped at time : 0 fs : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 157
338 
ISim O.87xd (signature 0x8ddf5b5d)
339 
WARNING: A WEBPACK license was found.
340 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
341 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
342 
This is a Lite version of ISim.
343 
# run 1000 ms
344 
Simulator is doing circuit initialization process.
345 
Stopped at time : 0 fs : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 157
346 
# run all
347 
Finished circuit initialization process.
348 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 157
349 
# run all
350 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
351 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
352 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
353 
Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 157
354 
# run all
355 
Stopped at time : 30 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
356 
# run all
357 
 
358 
** Failure:NONE. End of simulation.
359 
User(VHDL) Code Called Simulation Stop
360 
In process testUart_wishbone_slave.vhd:stim_proc
361 
 
362 
INFO: Simulator is stopped.
363 
ISim O.87xd (signature 0x8ddf5b5d)
364 
WARNING: A WEBPACK license was found.
365 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
366 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
367 
This is a Lite version of ISim.
368 
# run 1000 ms
369 
Simulator is doing circuit initialization process.
370 
Finished circuit initialization process.
371 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
372 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
373 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
374 
Stopped at time : 30 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 163
375 
ISim O.87xd (signature 0x8ddf5b5d)
376 
WARNING: A WEBPACK license was found.
377 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
378 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
379 
This is a Lite version of ISim.
380 
# run 1000 ms
381 
Simulator is doing circuit initialization process.
382 
Finished circuit initialization process.
383 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
384 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
385 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
386 
Stopped at time : 30 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 163
387 
ISim O.87xd (signature 0x8ddf5b5d)
388 
WARNING: A WEBPACK license was found.
389 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
390 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
391 
This is a Lite version of ISim.
392 
# run 1000 ms
393 
Simulator is doing circuit initialization process.
394 
Finished circuit initialization process.
395 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
396 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
397 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
398 
Stopped at time : 850 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
399 
# run all
400 
Stopped at time : 930 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
401 
# run all
402 
Stopped at time : 1010 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
403 
# run all
404 
Stopped at time : 1090 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
405 
# run all
406 
Stopped at time : 1170 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
407 
# run all
408 
 
409 
** Failure:NONE. End of simulation.
410 
User(VHDL) Code Called Simulation Stop
411 
In process testUart_wishbone_slave.vhd:stim_proc
412 
 
413 
INFO: Simulator is stopped.
414 
ISim O.87xd (signature 0x8ddf5b5d)
415 
WARNING: A WEBPACK license was found.
416 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
417 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
418 
This is a Lite version of ISim.
419 
# run 1000 ms
420 
Simulator is doing circuit initialization process.
421 
Finished circuit initialization process.
422 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
423 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
424 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
425 
 
426 
** Failure:NONE. End of simulation.
427 
User(VHDL) Code Called Simulation Stop
428 
In process testUart_wishbone_slave.vhd:stim_proc
429 
 
430 
INFO: Simulator is stopped.
431 
ISim O.87xd (signature 0x8ddf5b5d)
432 
WARNING: A WEBPACK license was found.
433 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
434 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
435 
This is a Lite version of ISim.
436 
# run 1000 ms
437 
Simulator is doing circuit initialization process.
438 
Finished circuit initialization process.
439 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
440 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
441 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
442 
 
443 
** Failure:NONE. End of simulation.
444 
User(VHDL) Code Called Simulation Stop
445 
In process testUart_wishbone_slave.vhd:stim_proc
446 
 
447 
INFO: Simulator is stopped.

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