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[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [IP_av2_complete_nomac_tb .vhd] - Blame information for rev 11

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1 11 pjf
--------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer:
4
--
5
-- Create Date:   13:54:32 06/04/2011
6
-- Design Name:   
7
-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IP_complete_nomac_tb.vhd
8
-- Project Name:  ip1
9
-- Target Device:  
10
-- Tool versions:  
11
-- Description:   
12
-- 
13
-- VHDL Test Bench Created by ISE for module: IP_complete_nomac
14
-- 
15
-- Dependencies:
16
-- 
17
-- Revision:
18
-- Revision 0.01 - File Created
19
-- Additional Comments:
20
--
21
-- Notes: 
22
-- This testbench has been automatically generated using types std_logic and
23
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
-- that these types always be used for the top-level I/O of a design in order
25
-- to guarantee that the testbench will bind correctly to the post-implementation 
26
-- simulation model.
27
--------------------------------------------------------------------------------
28
LIBRARY ieee;
29
USE ieee.std_logic_1164.ALL;
30
use IEEE.NUMERIC_STD.ALL;
31
use work.axi.all;
32
use work.ipv4_types.all;
33
use work.arp_types.all;
34
use work.arp;
35
use work.arpv2;
36
 
37
 
38
ENTITY IP_av2_complete_nomac_tb IS
39
END IP_av2_complete_nomac_tb;
40
 
41
 
42
 
43
--configuration main of IP_av2_complete_nomac_tb is
44
--      for behavior
45
--              for uut : IP_complete_nomac
46
--                      use configuration work.IP_complete_nomac.multi_slot_arp;
47
--              end for;
48
--      end for;
49
--end main;
50
 
51
ARCHITECTURE behavior OF IP_av2_complete_nomac_tb IS
52
 
53
    -- Component Declaration for the Unit Under Test (UUT)
54
 
55
    COMPONENT IP_complete_nomac
56
         generic (
57
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
58
                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
59
                        );
60
    Port (
61
                        -- IP Layer signals
62
                        ip_tx_start                             : in std_logic;
63
                        ip_tx                                           : in ipv4_tx_type;                                                              -- IP tx cxns
64
                        ip_tx_result                    : out std_logic_vector (1 downto 0);             -- tx status (changes during transmission)
65
                        ip_tx_data_out_ready    : out std_logic;                                                                        -- indicates IP TX is ready to take data
66
                        ip_rx_start                             : out std_logic;                                                                        -- indicates receipt of ip frame.
67
                        ip_rx                                           : out ipv4_rx_type;
68
                        -- system signals
69
                        rx_clk                                  : in  STD_LOGIC;
70
                        tx_clk                                  : in  STD_LOGIC;
71
                        reset                                   : in  STD_LOGIC;
72
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
73
                        our_mac_address                 : in std_logic_vector (47 downto 0);
74
                        control                                 : in ip_control_type;
75
                        -- status signals
76
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
77
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
78
                        -- MAC Transmitter
79
                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
80
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
81
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
82
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
83
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
84
                        -- MAC Receiver
85
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
86
                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
87
                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
88
                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
89
                        );
90
    END COMPONENT;
91
 
92
 
93
   --Inputs
94
   signal ip_tx_start : std_logic := '0';
95
   signal ip_tx : ipv4_tx_type;
96
 
97
   signal clk : std_logic := '0';
98
   signal reset : std_logic := '0';
99
   signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
100
   signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
101
   signal mac_tx_tready : std_logic := '0';
102
   signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
103
   signal mac_rx_tvalid : std_logic := '0';
104
   signal mac_rx_tlast : std_logic := '0';
105
        signal control                  : ip_control_type;
106
 
107
        --Outputs
108
        signal ip_tx_result : std_logic_vector (1 downto 0);                                             -- tx status (changes during transmission)
109
        signal ip_tx_data_out_ready     :  std_logic;                                                                   -- indicates IP TX is ready to take data
110
   signal ip_rx_start : std_logic;
111
   signal ip_rx : ipv4_rx_type;
112
   signal arp_pkt_count : std_logic_vector(7 downto 0);
113
   signal mac_tx_tdata : std_logic_vector(7 downto 0);
114
   signal mac_tx_tvalid : std_logic;
115
   signal mac_tx_tfirst : std_logic;
116
   signal mac_tx_tlast : std_logic;
117
   signal mac_rx_tready : std_logic;
118
 
119
   -- Clock period definitions
120
   constant clk_period : time := 8 ns;
121
 
122
BEGIN
123
 
124
        -- Instantiate the Unit Under Test (UUT)
125
   uut: IP_complete_nomac PORT MAP (
126
          ip_tx_start => ip_tx_start,
127
          ip_tx => ip_tx,
128
          ip_tx_result => ip_tx_result,
129
          ip_tx_data_out_ready => ip_tx_data_out_ready,
130
          ip_rx_start => ip_rx_start,
131
          ip_rx => ip_rx,
132
          rx_clk => clk,
133
          tx_clk => clk,
134
          reset => reset,
135
          our_ip_address => our_ip_address,
136
          our_mac_address => our_mac_address,
137
                         control => control,
138
          arp_pkt_count => arp_pkt_count,
139
          mac_tx_tdata => mac_tx_tdata,
140
          mac_tx_tvalid => mac_tx_tvalid,
141
          mac_tx_tready => mac_tx_tready,
142
                         mac_tx_tfirst => mac_tx_tfirst,
143
          mac_tx_tlast => mac_tx_tlast,
144
          mac_rx_tdata => mac_rx_tdata,
145
          mac_rx_tvalid => mac_rx_tvalid,
146
          mac_rx_tready => mac_rx_tready,
147
          mac_rx_tlast => mac_rx_tlast
148
        );
149
 
150
   -- Clock process definitions
151
   clk_process :process
152
   begin
153
                clk <= '1';
154
                wait for clk_period/2;
155
                clk <= '0';
156
                wait for clk_period/2;
157
   end process;
158
 
159
 
160
   -- Stimulus process
161
   stim_proc: process
162
   begin
163
      -- hold reset state for 100 ns.
164
      wait for 80 ns;
165
 
166
                our_ip_address <= x"c0a80509";          -- 192.168.5.9
167
                our_mac_address <= x"002320212223";
168
                control.arp_controls.clear_cache <= '0';
169
                ip_tx_start <= '0';
170
      mac_tx_tready <= '0';
171
 
172
                reset <= '1';
173
      wait for clk_period*10;
174
                reset <= '0';
175
      wait for clk_period*5;
176
 
177
                -- check reset conditions
178
                assert ip_tx_result = IPTX_RESULT_NONE                  report "ip_tx_result not initialised correctly on reset";
179
                assert ip_tx_data_out_ready = '0'                report "ip_tx_data_out_ready not initialised correctly on reset";
180
                assert mac_tx_tvalid = '0'                                               report "mac_tx_tvalid not initialised correctly on reset";
181
                assert mac_tx_tlast = '0'                                                        report " mac_tx_tlast not initialised correctly on reset";
182
                assert arp_pkt_count = x"00"                                            report " arp_pkt_count not initialised correctly on reset";
183
                assert ip_rx_start = '0'                                                         report "ip_rx_start not initialised correctly on reset";
184
                assert ip_rx.hdr.is_valid = '0'                                  report "ip_rx.hdr.is_valid not initialised correctly on reset";
185
                assert ip_rx.hdr.protocol = x"00"                               report "ip_rx.hdr.protocol not initialised correctly on reset";
186
                assert ip_rx.hdr.data_length = x"0000"                  report "ip_rx.hdr.data_length not initialised correctly on reset";
187
                assert ip_rx.hdr.src_ip_addr = x"00000000"      report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
188
                assert ip_rx.hdr.num_frame_errors = x"00"               report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
189
                assert ip_rx.data.data_in = x"00"                               report "ip_rx.data.data_in not initialised correctly on reset";
190
                assert ip_rx.data.data_in_valid = '0'                    report "ip_rx.data.data_in_valid not initialised correctly on reset";
191
                assert ip_rx.data.data_in_last = '0'                     report "ip_rx.data.data_in_last not initialised correctly on reset";
192
 
193
      -- insert stimulus here 
194
 
195
                ------------
196
                -- TEST 1 -- basic functional rx test with received ip pkt
197
                ------------
198
 
199
                report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
200
 
201
      mac_tx_tready <= '1';
202
                mac_rx_tvalid <= '1';
203
                -- dst MAC (bc)
204
                mac_rx_tdata <= x"00"; wait for clk_period;
205
                mac_rx_tdata <= x"23"; wait for clk_period;
206
                mac_rx_tdata <= x"20"; wait for clk_period;
207
                mac_rx_tdata <= x"21"; wait for clk_period;
208
                mac_rx_tdata <= x"22"; wait for clk_period;
209
                mac_rx_tdata <= x"23"; wait for clk_period;
210
                -- src MAC
211
                mac_rx_tdata <= x"00"; wait for clk_period;
212
                mac_rx_tdata <= x"23"; wait for clk_period;
213
                mac_rx_tdata <= x"18"; wait for clk_period;
214
                mac_rx_tdata <= x"29"; wait for clk_period;
215
                mac_rx_tdata <= x"26"; wait for clk_period;
216
                mac_rx_tdata <= x"7c"; wait for clk_period;
217
                -- type
218
                mac_rx_tdata <= x"08"; wait for clk_period;             -- IP pkt
219
                mac_rx_tdata <= x"00"; wait for clk_period;
220
                -- ver & HL / service type
221
                mac_rx_tdata <= x"45"; wait for clk_period;
222
                mac_rx_tdata <= x"00"; wait for clk_period;
223
                -- total len
224
                mac_rx_tdata <= x"00"; wait for clk_period;
225
                mac_rx_tdata <= x"18"; wait for clk_period;
226
                -- ID
227
                mac_rx_tdata <= x"00"; wait for clk_period;
228
                mac_rx_tdata <= x"00"; wait for clk_period;
229
                -- flags & frag
230
                mac_rx_tdata <= x"00"; wait for clk_period;
231
                mac_rx_tdata <= x"00"; wait for clk_period;
232
                -- TTL
233
                mac_rx_tdata <= x"00"; wait for clk_period;
234
                -- Protocol
235
                mac_rx_tdata <= x"11"; wait for clk_period;
236
                -- Header CKS
237
                mac_rx_tdata <= x"00"; wait for clk_period;
238
                mac_rx_tdata <= x"00"; wait for clk_period;
239
                -- SRC IP
240
                mac_rx_tdata <= x"c0"; wait for clk_period;
241
                mac_rx_tdata <= x"a8"; wait for clk_period;
242
                mac_rx_tdata <= x"05"; wait for clk_period;
243
                mac_rx_tdata <= x"01"; wait for clk_period;
244
                -- DST IP
245
                mac_rx_tdata <= x"c0"; wait for clk_period;
246
                mac_rx_tdata <= x"a8"; wait for clk_period;
247
                mac_rx_tdata <= x"05"; wait for clk_period;
248
                mac_rx_tdata <= x"09"; wait for clk_period;
249
 
250
                -- user data
251
                mac_rx_tdata <= x"24"; wait for clk_period;
252
 
253
                -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
254
                assert ip_rx.hdr.is_valid = '1'                                 report "T1: ip_rx.hdr.is_valid not set";
255
                assert ip_rx.hdr.protocol = x"11"                               report "T1: ip_rx.hdr.protocol not set correctly";
256
                assert ip_rx.hdr.data_length = x"0004"                  report "T1: ip_rx.hdr.data_length not set correctly";
257
                assert ip_rx.hdr.src_ip_addr = x"c0a80501"      report "T1: ip_rx.hdr.src_ip_addr not set correctly";
258
                assert ip_rx.hdr.num_frame_errors = x"00"               report "T1: ip_rx.hdr.num_frame_errors not set correctly";
259
                assert ip_rx.hdr.last_error_code = x"0"          report "T1: ip_rx.hdr.last_error_code not set correctly";
260
                assert ip_rx_start = '1'                                                        report "T1: ip_rx_start not set";
261
                assert ip_rx.data.data_in_valid = '1'                   report "T1: ip_rx.data.data_in_valid not set";
262
 
263
                mac_rx_tdata <= x"25"; wait for clk_period;
264
                mac_rx_tdata <= x"26"; wait for clk_period;
265
                mac_rx_tdata <= x"27"; mac_rx_tlast <= '1'; wait for clk_period;
266
 
267
                assert ip_rx.data.data_in_last = '1'                    report "T1: ip_rx.data.data_in_last not set";
268
 
269
 
270
                mac_rx_tdata <= x"00";
271
                mac_rx_tlast <= '0';
272
                mac_rx_tvalid <= '0';
273
                wait for clk_period;
274
 
275
                assert ip_rx.data.data_in_valid = '0'                    report "T1: ip_rx.data.data_in_valid not cleared";
276
                assert ip_rx.data.data_in_last = '0'                     report "T1: ip_rx.data.data_in_last not cleared";
277
                assert ip_rx.hdr.num_frame_errors = x"00"               report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
278
                assert ip_rx.hdr.last_error_code = x"0"          report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
279
                assert ip_rx_start = '0'                                                 report "T1: ip_rx_start not cleared";
280
 
281
                ------------
282
                -- TEST 2 -- respond with IP TX
283
                ------------
284
 
285
                report "T2: respond with IP TX";
286
 
287
                ip_tx.hdr.protocol <= x"35";
288
                ip_tx.hdr.data_length <= x"0006";
289
                ip_tx.hdr.dst_ip_addr <= x"c0123478";
290
                ip_tx.data.data_out_valid <= '0';
291
                ip_tx.data.data_out_last <= '0';
292
                wait for clk_period;
293
 
294
                ip_tx_start <= '1'; wait for clk_period;
295
 
296
                ip_tx_start <= '0'; wait for clk_period;
297
 
298
                assert ip_tx_result = IPTX_RESULT_SENDING               report "T2: result should be IPTX_RESULT_SENDING";
299
 
300
                wait for clk_period*2;
301
 
302
                assert ip_tx_data_out_ready = '0'                                report "T2: IP data out ready asserted too early";
303
 
304
                -- need to wait for ARP tx to complete
305
 
306
                wait for clk_period*50;
307
 
308
                assert mac_tx_tvalid = '0'                                               report "T2: mac_tx_tvalid not cleared after ARP tx";
309
                assert mac_tx_tlast = '0'                                                        report "T2: mac_tx_tlast not cleared after ARP tx";
310
 
311
                -- now create the ARP response (rx)
312
 
313
                -- Send the reply
314
                -- Send an ARP reply: x"c0123478" has mac 02:12:03:23:04:54
315
                mac_rx_tvalid <= '1';
316
                -- dst MAC (bc)
317
                mac_rx_tdata <= x"ff"; wait for clk_period;
318
                mac_rx_tdata <= x"ff"; wait for clk_period;
319
                mac_rx_tdata <= x"ff"; wait for clk_period;
320
                mac_rx_tdata <= x"ff"; wait for clk_period;
321
                mac_rx_tdata <= x"ff"; wait for clk_period;
322
                mac_rx_tdata <= x"ff"; wait for clk_period;
323
                -- src MAC
324
                mac_rx_tdata <= x"02"; wait for clk_period;
325
                mac_rx_tdata <= x"12"; wait for clk_period;
326
                mac_rx_tdata <= x"03"; wait for clk_period;
327
                mac_rx_tdata <= x"23"; wait for clk_period;
328
                mac_rx_tdata <= x"04"; wait for clk_period;
329
                mac_rx_tdata <= x"54"; wait for clk_period;
330
                -- type
331
                mac_rx_tdata <= x"08"; wait for clk_period;
332
                mac_rx_tdata <= x"06"; wait for clk_period;
333
                -- HW type
334
                mac_rx_tdata <= x"00"; wait for clk_period;
335
                mac_rx_tdata <= x"01"; wait for clk_period;
336
                -- Protocol type
337
                mac_rx_tdata <= x"08"; wait for clk_period;
338
                mac_rx_tdata <= x"00"; wait for clk_period;
339
                -- HW size
340
                mac_rx_tdata <= x"06"; wait for clk_period;
341
                -- protocol size
342
                mac_rx_tdata <= x"04"; wait for clk_period;
343
                -- Opcode
344
                mac_rx_tdata <= x"00"; wait for clk_period;
345
                mac_rx_tdata <= x"02"; wait for clk_period;
346
                -- Sender MAC
347
                mac_rx_tdata <= x"02"; wait for clk_period;
348
                mac_rx_tdata <= x"12"; wait for clk_period;
349
                mac_rx_tdata <= x"03"; wait for clk_period;
350
                mac_rx_tdata <= x"23"; wait for clk_period;
351
                mac_rx_tdata <= x"04"; wait for clk_period;
352
                mac_rx_tdata <= x"54"; wait for clk_period;
353
                -- Sender IP
354
                mac_rx_tdata <= x"c0"; wait for clk_period;
355
                mac_rx_tdata <= x"12"; wait for clk_period;
356
                mac_rx_tdata <= x"34"; wait for clk_period;
357
                mac_rx_tdata <= x"78"; wait for clk_period;
358
                -- Target MAC
359
                mac_rx_tdata <= x"00"; wait for clk_period;
360
                mac_rx_tdata <= x"23"; wait for clk_period;
361
                mac_rx_tdata <= x"20"; wait for clk_period;
362
                mac_rx_tdata <= x"21"; wait for clk_period;
363
                mac_rx_tdata <= x"22"; wait for clk_period;
364
                mac_rx_tdata <= x"23"; wait for clk_period;
365
                -- Target IP
366
                mac_rx_tdata <= x"c0"; wait for clk_period;
367
                mac_rx_tdata <= x"a8"; wait for clk_period;
368
                mac_rx_tdata <= x"05"; wait for clk_period;
369
                mac_rx_tdata <= x"09"; wait for clk_period;
370
                mac_rx_tdata <= x"00"; wait for clk_period;
371
                mac_rx_tdata <= x"00"; wait for clk_period;
372
                mac_rx_tdata <= x"00"; wait for clk_period;
373
                mac_rx_tlast <= '1';
374
                mac_rx_tdata <= x"00"; wait for clk_period;
375
                mac_rx_tlast <= '0';
376
                mac_rx_tvalid <= '0';
377
 
378
                wait until ip_tx_data_out_ready = '1';
379
 
380
                -- start to tx IP data
381
                ip_tx.data.data_out_valid <= '1';
382
                ip_tx.data.data_out <= x"56"; wait for clk_period;
383
                ip_tx.data.data_out <= x"57"; wait for clk_period;
384
                ip_tx.data.data_out <= x"58"; wait for clk_period;
385
                ip_tx.data.data_out <= x"59"; wait for clk_period;
386
                ip_tx.data.data_out <= x"5a"; wait for clk_period;
387
 
388
                ip_tx.data.data_out <= x"5b";
389
                ip_tx.data.data_out_last <= '1';
390
                wait for clk_period;
391
 
392
                assert mac_tx_tlast = '1'                                                       report "T2: mac_tx_tlast not set on last byte";
393
 
394
                wait for clk_period;
395
 
396
                ip_tx.data.data_out_valid <= '0';
397
                ip_tx.data.data_out_last <= '0';
398
                wait for clk_period*2;
399
 
400
                assert ip_tx_result = IPTX_RESULT_SENT                  report "T2: result should be SENT";
401
                wait for clk_period*10;
402
 
403
                ------------
404
                -- TEST 3 -- Check that sending to the same IP addr doesnt cause an ARP req as the addr is cached
405
                ------------
406
 
407
                report "T3: Send 2nd IP TX to same IP addr - should not need to do ARP tx/rx";
408
                ip_tx.hdr.protocol <= x"35";
409
                ip_tx.hdr.data_length <= x"0006";
410
                ip_tx.hdr.dst_ip_addr <= x"c0123478";
411
                ip_tx.data.data_out_valid <= '0';
412
                ip_tx.data.data_out_last <= '0';
413
                wait for clk_period;
414
                ip_tx_start <= '1'; wait for clk_period;
415
                ip_tx_start <= '0'; wait for clk_period;
416
                assert ip_tx_result = IPTX_RESULT_SENDING               report "T3: result should be IPTX_RESULT_SENDING";
417
                wait for clk_period*2;
418
                assert ip_tx_data_out_ready = '0'                                report "T3: IP data out ready asserted too early";
419
                wait until ip_tx_data_out_ready = '1';
420
 
421
                -- start to tx IP data
422
                ip_tx.data.data_out_valid <= '1';
423
                ip_tx.data.data_out <= x"81"; wait for clk_period;
424
                ip_tx.data.data_out <= x"83"; wait for clk_period;
425
                ip_tx.data.data_out <= x"85"; wait for clk_period;
426
                ip_tx.data.data_out <= x"87"; wait for clk_period;
427
                ip_tx.data.data_out <= x"89"; wait for clk_period;
428
 
429
                ip_tx.data.data_out <= x"8b";
430
                ip_tx.data.data_out_last <= '1';
431
                wait for clk_period;
432
 
433
                assert mac_tx_tlast = '1'                                                       report "T3: mac_tx_tlast not set on last byte";
434
 
435
                wait for clk_period;
436
 
437
                ip_tx.data.data_out_valid <= '0';
438
                ip_tx.data.data_out_last <= '0';
439
                wait for clk_period*2;
440
 
441
                assert ip_tx_result = IPTX_RESULT_SENT                  report "T3: result should be SENT";
442
                wait for clk_period*2;
443
 
444
 
445
 
446
                report "-- end of tests --";
447
 
448
      wait;
449
   end process;
450
 
451
END;

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