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[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [IPv4_TX_tb.vhd] - Blame information for rev 18

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1 18 pjf
--------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer:
4
--
5
-- Create Date:   09:35:58 06/03/2011
6
-- Design Name:   
7
-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
8
-- Project Name:  ip1
9
-- Target Device:  
10
-- Tool versions:  
11
-- Description:   
12
-- 
13
-- VHDL Test Bench Created by ISE for module: IPv4_TX
14
-- 
15
-- Dependencies:
16
-- 
17
-- Revision:
18
-- Revision 0.01 - File Created
19
-- Revision 0.02 - Added test for IP broadcast tx
20
-- Additional Comments:
21
--
22
-- Notes: 
23
-- This testbench has been automatically generated using types std_logic and
24
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
25
-- that these types always be used for the top-level I/O of a design in order
26
-- to guarantee that the testbench will bind correctly to the post-implementation 
27
-- simulation model.
28
--------------------------------------------------------------------------------
29
library ieee;
30
use ieee.std_logic_1164.all;
31
use IEEE.NUMERIC_STD.all;
32
use work.axi.all;
33
use work.ipv4_types.all;
34
use work.arp_types.all;
35 2 pjf
 
36 18 pjf
 
37
entity IPv4_TX_tb is
38
end IPv4_TX_tb;
39
 
40
architecture behavior of IPv4_TX_tb is
41
 
42
  -- Component Declaration for the Unit Under Test (UUT)
43
 
44
  component IPv4_TX
45
    port(
46
      -- IP Layer signals
47
      ip_tx_start          : in  std_logic;
48
      ip_tx                : in  ipv4_tx_type;                   -- IP tx cxns
49
      ip_tx_result         : out std_logic_vector (1 downto 0);  -- tx status (changes during transmission)
50
      ip_tx_data_out_ready : out std_logic;  -- indicates IP TX is ready to take data
51
 
52
      -- system signals
53
      clk                : in  std_logic;  -- same clock used to clock mac data and ip data
54
      reset              : in  std_logic;
55
      our_ip_address     : in  std_logic_vector (31 downto 0);
56
      our_mac_address    : in  std_logic_vector (47 downto 0);
57
      -- ARP lookup signals
58
      arp_req_req        : out arp_req_req_type;
59
      arp_req_rslt       : in  arp_req_rslt_type;
60
      -- MAC layer TX signals
61
      mac_tx_req         : out std_logic;  -- indicates that ip wants access to channel (stays up for as long as tx)
62
      mac_tx_granted     : in  std_logic;  -- indicates that access to channel has been granted            
63
      mac_data_out_ready : in  std_logic;  -- indicates system ready to consume data
64
      mac_data_out_valid : out std_logic;  -- indicates data out is valid
65
      mac_data_out_first : out std_logic;  -- with data out valid indicates the first byte of a frame
66
      mac_data_out_last  : out std_logic;  -- with data out valid indicates the last byte of a frame
67
      mac_data_out       : out std_logic_vector (7 downto 0)  -- ethernet frame (from dst mac addr through to last byte of frame)      
68
      );
69
  end component;
70
 
71
 
72
  --Inputs
73
  signal ip_tx_start        : std_logic                     := '0';
74
  signal ip_tx              : ipv4_tx_type;
75
  signal clk                : std_logic                     := '0';
76
  signal reset              : std_logic                     := '0';
77
  signal our_ip_address     : std_logic_vector(31 downto 0) := (others => '0');
78
  signal our_mac_address    : std_logic_vector(47 downto 0) := (others => '0');
79
  signal mac_tx_granted     : std_logic                     := '0';
80
  signal mac_data_out_ready : std_logic                     := '0';
81
  signal arp_req_rslt       : arp_req_rslt_type;
82
 
83
  --Outputs
84
  signal ip_tx_result         : std_logic_vector (1 downto 0);  -- tx status (changes during transmission)
85
  signal ip_tx_data_out_ready : std_logic;  -- indicates IP TX is ready to take data
86
  signal mac_tx_req           : std_logic;
87
  signal mac_data_out_valid   : std_logic;
88
  signal mac_data_out_last    : std_logic;
89
  signal mac_data_out_first   : std_logic;
90
  signal mac_data_out         : std_logic_vector(7 downto 0);
91
  signal arp_req_req          : arp_req_req_type;
92
 
93
  -- Clock period definitions
94
  constant clk_period : time := 8 ns;
95
 
96
begin
97
 
98
  -- Instantiate the Unit Under Test (UUT)
99
  uut : IPv4_TX port map (
100
    ip_tx_start          => ip_tx_start,
101
    ip_tx                => ip_tx,
102
    ip_tx_result         => ip_tx_result,
103
    ip_tx_data_out_ready => ip_tx_data_out_ready,
104
    clk                  => clk,
105
    reset                => reset,
106
    our_ip_address       => our_ip_address,
107
    our_mac_address      => our_mac_address,
108
    arp_req_req          => arp_req_req,
109
    arp_req_rslt         => arp_req_rslt,
110
    mac_tx_req           => mac_tx_req,
111
    mac_tx_granted       => mac_tx_granted,
112
    mac_data_out_ready   => mac_data_out_ready,
113
    mac_data_out_valid   => mac_data_out_valid,
114
    mac_data_out_first   => mac_data_out_first,
115
    mac_data_out_last    => mac_data_out_last,
116
    mac_data_out         => mac_data_out
117
    );
118
 
119
  -- Clock process definitions
120
  clk_process : process
121
  begin
122
    clk <= '0';
123
    wait for clk_period/2;
124
    clk <= '1';
125
    wait for clk_period/2;
126
  end process;
127
 
128
 
129
  -- Stimulus process
130
  stim_proc : process
131
  begin
132
    our_ip_address            <= x"c0a80509";  -- 192.168.5.9
133
    our_mac_address           <= x"002320212223";
134
    ip_tx_start               <= '0';
135
    mac_tx_granted            <= '0';
136
    mac_data_out_ready        <= '0';
137
    ip_tx.data.data_out_valid <= '0';
138
    ip_tx.data.data_out_last  <= '0';
139
    arp_req_rslt.got_mac      <= '0';
140
    arp_req_rslt.got_err      <= '0';
141
    arp_req_rslt.mac          <= (others => '0');
142
 
143
    reset <= '1';
144
    wait for clk_period*10;
145
    reset <= '0';
146
    wait until clk = '1';
147
    wait for clk_period*5;
148
    wait until clk = '1';
149
 
150
    -- check reset conditions
151
    assert arp_req_req.lookup_req = '0' report "arp_req_req.lookup_req not initialised correctly on reset";
152
    assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
153
    assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
154
    assert mac_tx_req = '0' report "mac_tx_req not initialised correctly on reset";
155
    assert mac_data_out_valid = '0' report "mac_data_out_valid not initialised correctly on reset";
156
    assert mac_data_out_last = '0' report "mac_data_out_last not initialised correctly on reset";
157
 
158
    -- insert stimulus here 
159
 
160
    ------------
161
    -- TEST 1 -- basic functional tx test with some delays for arp and chn access
162
    ------------
163
 
164
    report "T1: basic functional tx test with some delays for arp and chn access";
165
 
166
    ip_tx.hdr.protocol    <= x"35";
167
    ip_tx.hdr.data_length <= x"0008";
168
    ip_tx.hdr.dst_ip_addr <= x"c0123478";
169
    ip_tx_start           <= '1';
170
    wait until clk = '1';
171
    ip_tx_start           <= '0';
172
    arp_req_rslt.got_mac  <= '0';
173
    arp_req_rslt.got_err  <= '0';
174
 
175
    wait until clk = '1';
176
    assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
177
    assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
178
 
179
    wait for clk_period*10;             -- simulate arp lookup time
180
    wait until clk = '1';
181
    arp_req_rslt.mac     <= x"050423271016";
182
    arp_req_rslt.got_mac <= '1';
183
 
184
    wait until clk = '1';
185
    wait until clk = '1';
186
    assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
187
    assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
188
 
189
    wait for clk_period*10;             -- simulate mac chn access time
190
    wait until clk = '1';
191
    mac_tx_granted     <= '1';
192
    wait until clk = '1'; wait until clk = '1';     mac_data_out_ready <= '1';
193
    assert mac_data_out_valid = '0' report "T1: mac_data_out_valid asserted too early";
194
 
195
    wait until clk = '1';
196
 
197
    assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
198
    wait until clk = '1';
199
    assert mac_data_out_valid = '1' report "T1: mac_data_out_valid not asserted";
200
 
201
    -- wait until in eth hdr
202
    wait for clk_period*3;
203
    wait until clk = '1';
204
    -- go mac not ready for 2 clocks
205
    mac_data_out_ready <= '0';
206
    wait until clk = '1'; wait until clk = '1';     wait until clk = '1';
207
    mac_data_out_ready <= '1';
208
 
209
 
210
    wait until ip_tx_data_out_ready = '1';
211
    wait until clk = '1';
212
 
213
    -- start to tx IP data
214
    ip_tx.data.data_out_valid <= '1';
215
    ip_tx.data.data_out       <= x"56"; wait until clk = '1';
216
    -- delay data in for 1 clk cycle
217
    ip_tx.data.data_out_valid <= '0';
218
    ip_tx.data.data_out       <= x"57"; wait until clk = '1';
219
    ip_tx.data.data_out_valid <= '1'; wait until clk = '1';
220
    ip_tx.data.data_out       <= x"58"; wait until clk = '1';
221
    ip_tx.data.data_out       <= x"59";     wait until clk = '1';
222
--wait for clk_period;
223
 
224
    -- delay mac ready for 2 clk cycles
225
    mac_data_out_ready  <= '0';
226
    ip_tx.data.data_out <= x"5a";    wait until clk = '1';
227
--wait for clk_period;
228
    assert ip_tx_data_out_ready = '0' report "T1: ip_tx_data_out_ready not cleared when mac not ready";
229
 
230
    ip_tx.data.data_out <= x"5a";     wait until clk = '1';
231
--wait for clk_period;
232
    mac_data_out_ready  <= '1';
233
    wait until ip_tx_data_out_ready = '1';
234
    wait until clk = '1';
235
--    wait for clk_period;
236
    assert ip_tx_data_out_ready = '1' report "T1: ip_tx_data_out_ready not set when mac ready";
237
    ip_tx.data.data_out <= x"5b"; wait until clk = '1';
238
    ip_tx.data.data_out <= x"5c"; wait until clk = '1';
239
 
240
    ip_tx.data.data_out      <= x"5d";
241
    ip_tx.data.data_out_last <= '1';
242
    wait until clk = '1';
243
    assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
244
 
245
    ip_tx.data.data_out_valid <= '0';
246
    ip_tx.data.data_out_last  <= '0';
247
    wait until clk = '1'; wait until clk = '1';
248
    assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
249
    assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
250
 
251
    mac_tx_granted <= '0';
252
    wait until clk = '1'; wait until clk = '1';
253
    ------------
254
    -- TEST 2 -- basic functional tx test with no delays for arp and chn access
255
    ------------
256
 
257
    report "T2: basic functional tx test with no delays for arp and chn access";
258
 
259
    ip_tx.hdr.protocol    <= x"11";
260
    ip_tx.hdr.data_length <= x"0006";
261
    ip_tx.hdr.dst_ip_addr <= x"c0123478";
262
    ip_tx_start           <= '1';
263
    wait until clk = '1';
264
    ip_tx_start           <= '0'; wait until clk = '1';
265
    arp_req_rslt.got_mac  <= '0';
266
 
267
    assert arp_req_req.lookup_req = '1' report "T2: lookup_req not set on tx start";
268
    assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING";
269
 
270
    wait until clk = '1';                -- simulate arp lookup time
271
    arp_req_rslt.mac     <= x"050423271016";
272
    arp_req_rslt.got_mac <= '1';
273
 
274
    wait until clk = '1'; wait until clk = '1';
275
    assert arp_req_req.lookup_req = '0' report "T2: lookup_req not clear after setting";
276
    assert mac_tx_req = '1' report "T2: mac_tx_req not set after getting mac";
277
 
278
    wait until clk = '1';                -- simulate mac chn access time
279
    mac_tx_granted     <= '1';
280
    wait until clk = '1'; wait until clk = '1';     mac_data_out_ready <= '1';
281
 
282
    assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
283
 
284
    wait until ip_tx_data_out_ready = '1';
285
 
286
    -- start to tx IP data
287
    ip_tx.data.data_out_valid <= '1';
288
    ip_tx.data.data_out       <= x"c1"; wait until clk = '1';
289
    ip_tx.data.data_out       <= x"c2"; wait until clk = '1';
290
    ip_tx.data.data_out       <= x"c3"; wait until clk = '1';
291
    ip_tx.data.data_out       <= x"c4"; wait until clk = '1';
292
    ip_tx.data.data_out       <= x"c5"; wait until clk = '1';
293
 
294
    ip_tx.data.data_out      <= x"c6";
295
    ip_tx.data.data_out_last <= '1';
296
    wait until clk = '1';
297
 
298
    assert mac_data_out_last = '1' report "T2: mac_datda_out_last not set on last byte";
299
 
300
 
301
    ip_tx.data.data_out_valid <= '0';
302
    ip_tx.data.data_out_last  <= '0';
303
    wait until clk = '1'; wait until clk = '1';
304
    assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be IPTX_RESULT_SENT";
305
    assert mac_tx_req = '0' report "T2: mac_tx_req held on too long after TX";
306
 
307
    mac_tx_granted <= '0';
308
    wait until clk = '1'; wait until clk = '1';
309
    ------------
310
    -- TEST 3 -- tx test for IP broadcast, should be no arp req
311
    ------------
312
 
313
    report "T3: tx test for IP broadcast, should be no arp req";
314
 
315
    ip_tx.hdr.protocol    <= x"11";
316
    ip_tx.hdr.data_length <= x"0006";
317
    ip_tx.hdr.dst_ip_addr <= x"ffffffff";
318
    ip_tx_start           <= '1';
319
    wait until clk = '1';
320
    ip_tx_start           <= '0'; wait until clk = '1';
321
    arp_req_rslt.got_mac  <= '0';
322
 
323
    assert arp_req_req.lookup_req = '0' report "T3: its trying to do an ARP req tx start";
324
    assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING";
325
 
326
    wait until clk = '1';                -- simulate mac chn access time
327
    mac_tx_granted     <= '1';
328
    wait until clk = '1'; wait until clk = '1';     mac_data_out_ready <= '1';
329
 
330
    assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early";
331
 
332
    wait until ip_tx_data_out_ready = '1';
333
 
334
    -- start to tx IP data
335
    ip_tx.data.data_out_valid <= '1';
336
    ip_tx.data.data_out       <= x"c1"; wait until clk = '1';
337
    ip_tx.data.data_out       <= x"c2"; wait until clk = '1';
338
    ip_tx.data.data_out       <= x"c3"; wait until clk = '1';
339
    ip_tx.data.data_out       <= x"c4"; wait until clk = '1';
340
    ip_tx.data.data_out       <= x"c5"; wait until clk = '1';
341
 
342
    ip_tx.data.data_out      <= x"c6";
343
    ip_tx.data.data_out_last <= '1';
344
    wait until clk = '1';
345
 
346
    assert mac_data_out_last = '1' report "T3: mac_datda_out_last not set on last byte";
347
 
348
 
349
    ip_tx.data.data_out_valid <= '0';
350
    ip_tx.data.data_out_last  <= '0';
351
    wait until clk = '1'; wait until clk = '1';
352
    assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be IPTX_RESULT_SENT";
353
    assert mac_tx_req = '0' report "T3: mac_tx_req held on too long after TX";
354
 
355
    mac_tx_granted <= '0';
356
    wait until clk = '1'; wait until clk = '1';
357
 
358
    report "--- end of tests ---";
359
 
360
    wait;
361
  end process;
362
 
363
end;

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