OpenCores
URL https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk

Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [IPv4_TX_tb.vhd] - Blame information for rev 29

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 pjf
--------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer:
4
--
5
-- Create Date:   09:35:58 06/03/2011
6
-- Design Name:   
7
-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
8
-- Project Name:  ip1
9
-- Target Device:  
10
-- Tool versions:  
11
-- Description:   
12
-- 
13
-- VHDL Test Bench Created by ISE for module: IPv4_TX
14
-- 
15
-- Dependencies:
16
-- 
17
-- Revision:
18
-- Revision 0.01 - File Created
19
-- Revision 0.02 - Added test for IP broadcast tx
20
-- Additional Comments:
21
--
22
-- Notes: 
23
-- This testbench has been automatically generated using types std_logic and
24
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
25
-- that these types always be used for the top-level I/O of a design in order
26
-- to guarantee that the testbench will bind correctly to the post-implementation 
27
-- simulation model.
28
--------------------------------------------------------------------------------
29
library ieee;
30
use ieee.std_logic_1164.all;
31
use IEEE.NUMERIC_STD.all;
32
use work.axi.all;
33
use work.ipv4_types.all;
34
use work.arp_types.all;
35 2 pjf
 
36 18 pjf
 
37
entity IPv4_TX_tb is
38
end IPv4_TX_tb;
39
 
40
architecture behavior of IPv4_TX_tb is
41
 
42
  -- Component Declaration for the Unit Under Test (UUT)
43
 
44
  component IPv4_TX
45
    port(
46
      -- IP Layer signals
47
      ip_tx_start          : in  std_logic;
48
      ip_tx                : in  ipv4_tx_type;                   -- IP tx cxns
49
      ip_tx_result         : out std_logic_vector (1 downto 0);  -- tx status (changes during transmission)
50
      ip_tx_data_out_ready : out std_logic;  -- indicates IP TX is ready to take data
51
 
52
      -- system signals
53
      clk                : in  std_logic;  -- same clock used to clock mac data and ip data
54
      reset              : in  std_logic;
55
      our_ip_address     : in  std_logic_vector (31 downto 0);
56
      our_mac_address    : in  std_logic_vector (47 downto 0);
57
      -- ARP lookup signals
58
      arp_req_req        : out arp_req_req_type;
59
      arp_req_rslt       : in  arp_req_rslt_type;
60
      -- MAC layer TX signals
61
      mac_tx_req         : out std_logic;  -- indicates that ip wants access to channel (stays up for as long as tx)
62
      mac_tx_granted     : in  std_logic;  -- indicates that access to channel has been granted            
63
      mac_data_out_ready : in  std_logic;  -- indicates system ready to consume data
64
      mac_data_out_valid : out std_logic;  -- indicates data out is valid
65
      mac_data_out_first : out std_logic;  -- with data out valid indicates the first byte of a frame
66
      mac_data_out_last  : out std_logic;  -- with data out valid indicates the last byte of a frame
67
      mac_data_out       : out std_logic_vector (7 downto 0)  -- ethernet frame (from dst mac addr through to last byte of frame)      
68
      );
69
  end component;
70
 
71
 
72
  --Inputs
73
  signal ip_tx_start        : std_logic                     := '0';
74
  signal ip_tx              : ipv4_tx_type;
75
  signal clk                : std_logic                     := '0';
76
  signal reset              : std_logic                     := '0';
77
  signal our_ip_address     : std_logic_vector(31 downto 0) := (others => '0');
78
  signal our_mac_address    : std_logic_vector(47 downto 0) := (others => '0');
79
  signal mac_tx_granted     : std_logic                     := '0';
80
  signal mac_data_out_ready : std_logic                     := '0';
81
  signal arp_req_rslt       : arp_req_rslt_type;
82
 
83
  --Outputs
84
  signal ip_tx_result         : std_logic_vector (1 downto 0);  -- tx status (changes during transmission)
85
  signal ip_tx_data_out_ready : std_logic;  -- indicates IP TX is ready to take data
86
  signal mac_tx_req           : std_logic;
87
  signal mac_data_out_valid   : std_logic;
88
  signal mac_data_out_last    : std_logic;
89
  signal mac_data_out_first   : std_logic;
90
  signal mac_data_out         : std_logic_vector(7 downto 0);
91
  signal arp_req_req          : arp_req_req_type;
92
 
93
  -- Clock period definitions
94
  constant clk_period : time := 8 ns;
95
 
96
begin
97
 
98
  -- Instantiate the Unit Under Test (UUT)
99
  uut : IPv4_TX port map (
100
    ip_tx_start          => ip_tx_start,
101
    ip_tx                => ip_tx,
102
    ip_tx_result         => ip_tx_result,
103
    ip_tx_data_out_ready => ip_tx_data_out_ready,
104
    clk                  => clk,
105
    reset                => reset,
106
    our_ip_address       => our_ip_address,
107
    our_mac_address      => our_mac_address,
108
    arp_req_req          => arp_req_req,
109
    arp_req_rslt         => arp_req_rslt,
110
    mac_tx_req           => mac_tx_req,
111
    mac_tx_granted       => mac_tx_granted,
112
    mac_data_out_ready   => mac_data_out_ready,
113
    mac_data_out_valid   => mac_data_out_valid,
114
    mac_data_out_first   => mac_data_out_first,
115
    mac_data_out_last    => mac_data_out_last,
116
    mac_data_out         => mac_data_out
117
    );
118
 
119
  -- Clock process definitions
120
  clk_process : process
121
  begin
122
    clk <= '0';
123
    wait for clk_period/2;
124
    clk <= '1';
125
    wait for clk_period/2;
126
  end process;
127
 
128
 
129
  -- Stimulus process
130
  stim_proc : process
131
  begin
132
    our_ip_address            <= x"c0a80509";  -- 192.168.5.9
133
    our_mac_address           <= x"002320212223";
134
    ip_tx_start               <= '0';
135
    mac_tx_granted            <= '0';
136
    mac_data_out_ready        <= '0';
137
    ip_tx.data.data_out_valid <= '0';
138
    ip_tx.data.data_out_last  <= '0';
139
    arp_req_rslt.got_mac      <= '0';
140
    arp_req_rslt.got_err      <= '0';
141
    arp_req_rslt.mac          <= (others => '0');
142
 
143
    reset <= '1';
144
    wait for clk_period*10;
145
    reset <= '0';
146
    wait until clk = '1';
147
    wait for clk_period*5;
148
    wait until clk = '1';
149
 
150
    -- check reset conditions
151
    assert arp_req_req.lookup_req = '0' report "arp_req_req.lookup_req not initialised correctly on reset";
152
    assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
153
    assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
154
    assert mac_tx_req = '0' report "mac_tx_req not initialised correctly on reset";
155
    assert mac_data_out_valid = '0' report "mac_data_out_valid not initialised correctly on reset";
156
    assert mac_data_out_last = '0' report "mac_data_out_last not initialised correctly on reset";
157
 
158
    -- insert stimulus here 
159
 
160
    ------------
161
    -- TEST 1 -- basic functional tx test with some delays for arp and chn access
162
    ------------
163
 
164
    report "T1: basic functional tx test with some delays for arp and chn access";
165
 
166
    ip_tx.hdr.protocol    <= x"35";
167
    ip_tx.hdr.data_length <= x"0008";
168
    ip_tx.hdr.dst_ip_addr <= x"c0123478";
169
    ip_tx_start           <= '1';
170
    wait until clk = '1';
171
    ip_tx_start           <= '0';
172
    arp_req_rslt.got_mac  <= '0';
173
    arp_req_rslt.got_err  <= '0';
174
 
175
    wait until clk = '1';
176
    assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
177
    assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
178
 
179
    wait for clk_period*10;             -- simulate arp lookup time
180
    wait until clk = '1';
181
    arp_req_rslt.mac     <= x"050423271016";
182
    arp_req_rslt.got_mac <= '1';
183
 
184
    wait until clk = '1';
185
    wait until clk = '1';
186
    assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
187
    assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
188
 
189
    wait for clk_period*10;             -- simulate mac chn access time
190
    wait until clk = '1';
191
    mac_tx_granted     <= '1';
192
    wait until clk = '1'; wait until clk = '1';     mac_data_out_ready <= '1';
193
    assert mac_data_out_valid = '0' report "T1: mac_data_out_valid asserted too early";
194
 
195
    wait until clk = '1';
196
 
197
    assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
198
    wait until clk = '1';
199
    assert mac_data_out_valid = '1' report "T1: mac_data_out_valid not asserted";
200
 
201
    -- wait until in eth hdr
202
    wait for clk_period*3;
203
    wait until clk = '1';
204
    -- go mac not ready for 2 clocks
205
    mac_data_out_ready <= '0';
206
    wait until clk = '1'; wait until clk = '1';     wait until clk = '1';
207
    mac_data_out_ready <= '1';
208
 
209
 
210
    wait until ip_tx_data_out_ready = '1';
211
    wait until clk = '1';
212
 
213
    -- start to tx IP data
214
    ip_tx.data.data_out_valid <= '1';
215
    ip_tx.data.data_out       <= x"56"; wait until clk = '1';
216
    -- delay data in for 1 clk cycle
217
    ip_tx.data.data_out_valid <= '0';
218
    ip_tx.data.data_out       <= x"57"; wait until clk = '1';
219
    ip_tx.data.data_out_valid <= '1'; wait until clk = '1';
220
    ip_tx.data.data_out       <= x"58"; wait until clk = '1';
221
    ip_tx.data.data_out       <= x"59";     wait until clk = '1';
222
--wait for clk_period;
223
 
224
    -- delay mac ready for 2 clk cycles
225
    mac_data_out_ready  <= '0';
226
    ip_tx.data.data_out <= x"5a";    wait until clk = '1';
227
--wait for clk_period;
228
    assert ip_tx_data_out_ready = '0' report "T1: ip_tx_data_out_ready not cleared when mac not ready";
229
 
230
    ip_tx.data.data_out <= x"5a";     wait until clk = '1';
231
--wait for clk_period;
232
    mac_data_out_ready  <= '1';
233
    wait until ip_tx_data_out_ready = '1';
234
    wait until clk = '1';
235
--    wait for clk_period;
236
    assert ip_tx_data_out_ready = '1' report "T1: ip_tx_data_out_ready not set when mac ready";
237
    ip_tx.data.data_out <= x"5b"; wait until clk = '1';
238
    ip_tx.data.data_out <= x"5c"; wait until clk = '1';
239
 
240
    ip_tx.data.data_out      <= x"5d";
241
    ip_tx.data.data_out_last <= '1';
242
    wait until clk = '1';
243
    assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
244
 
245
    ip_tx.data.data_out_valid <= '0';
246
    ip_tx.data.data_out_last  <= '0';
247
    wait until clk = '1'; wait until clk = '1';
248
    assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
249
    assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
250
 
251
    mac_tx_granted <= '0';
252
    wait until clk = '1'; wait until clk = '1';
253
    ------------
254
    -- TEST 2 -- basic functional tx test with no delays for arp and chn access
255
    ------------
256
 
257
    report "T2: basic functional tx test with no delays for arp and chn access";
258
 
259
    ip_tx.hdr.protocol    <= x"11";
260
    ip_tx.hdr.data_length <= x"0006";
261
    ip_tx.hdr.dst_ip_addr <= x"c0123478";
262
    ip_tx_start           <= '1';
263
    wait until clk = '1';
264
    ip_tx_start           <= '0'; wait until clk = '1';
265
    arp_req_rslt.got_mac  <= '0';
266
 
267
    assert arp_req_req.lookup_req = '1' report "T2: lookup_req not set on tx start";
268
    assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING";
269
 
270
    wait until clk = '1';                -- simulate arp lookup time
271
    arp_req_rslt.mac     <= x"050423271016";
272
    arp_req_rslt.got_mac <= '1';
273
 
274
    wait until clk = '1'; wait until clk = '1';
275
    assert arp_req_req.lookup_req = '0' report "T2: lookup_req not clear after setting";
276
    assert mac_tx_req = '1' report "T2: mac_tx_req not set after getting mac";
277
 
278
    wait until clk = '1';                -- simulate mac chn access time
279
    mac_tx_granted     <= '1';
280 29 pjf
    wait until clk = '1'; wait until falling_edge(clk);     mac_data_out_ready <= '1';
281 18 pjf
 
282
    assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
283
 
284 29 pjf
         -- check data output to MAC layer
285
         if mac_data_out_valid = '0' then
286
                report "T2: waiting for mac_data_out_valid";
287
                wait until mac_data_out_valid = '1';
288
                wait until falling_edge(clk);
289
         end if;
290
         report "T2: got mac_data_out_valid";
291
         assert mac_data_out = x"05"    report "T2a1: mac_data_out incorrect";  wait for clk_period;
292
         assert mac_data_out = x"04"    report "T2a2: mac_data_out incorrect";  wait for clk_period;
293
         assert mac_data_out = x"23"    report "T2a3: mac_data_out incorrect";  wait for clk_period;
294
         assert mac_data_out = x"27"    report "T2a4: mac_data_out incorrect";  wait for clk_period;
295
         assert mac_data_out = x"10"    report "T2a5: mac_data_out incorrect";  wait for clk_period;
296
         assert mac_data_out = x"16"    report "T2a6: mac_data_out incorrect";  wait for clk_period;
297
         assert mac_data_out = x"00"    report "T2b1: mac_data_out incorrect";  wait for clk_period;
298
         assert mac_data_out = x"23"    report "T2b2: mac_data_out incorrect";  wait for clk_period;
299
         assert mac_data_out = x"20"    report "T2b3: mac_data_out incorrect";  wait for clk_period;
300
         assert mac_data_out = x"21"    report "T2b4: mac_data_out incorrect";  wait for clk_period;
301
         assert mac_data_out = x"22"    report "T2b5: mac_data_out incorrect";  wait for clk_period;
302
         assert mac_data_out = x"23"    report "T2b6: mac_data_out incorrect";  wait for clk_period;
303
         assert mac_data_out = x"08"    report "T2c1: mac_data_out incorrect";  wait for clk_period;
304
         assert mac_data_out = x"00"    report "T2c2: mac_data_out incorrect";  wait for clk_period;
305
         assert mac_data_out = x"45"    report "T2d1: mac_data_out incorrect";  wait for clk_period;
306
         assert mac_data_out = x"00"    report "T2d2: mac_data_out incorrect";  wait for clk_period;
307
         assert mac_data_out = x"00"    report "T2d3: mac_data_out incorrect";  wait for clk_period;
308
         assert mac_data_out = x"1a"    report "T2d4: mac_data_out incorrect";  wait for clk_period;
309
         assert mac_data_out = x"00"    report "T2e1: mac_data_out incorrect";  wait for clk_period;
310
         assert mac_data_out = x"00"    report "T2e2: mac_data_out incorrect";  wait for clk_period;
311
         assert mac_data_out = x"00"    report "T2e3: mac_data_out incorrect";  wait for clk_period;
312
         assert mac_data_out = x"00"    report "T2e4: mac_data_out incorrect";  wait for clk_period;
313
         assert mac_data_out = x"80"    report "T2f1: mac_data_out incorrect";  wait for clk_period;
314
         assert mac_data_out = x"11"    report "T2f2: mac_data_out incorrect";  wait for clk_period;
315
         assert mac_data_out = x"80"    report "T2f3: mac_data_out incorrect";  wait for clk_period;
316
         assert mac_data_out = x"97"    report "T2f4: mac_data_out incorrect";  wait for clk_period;
317
 
318
         if ip_tx_data_out_ready = '0' then
319
                wait until ip_tx_data_out_ready = '1';
320
                wait until falling_edge(clk);
321
         end if;
322 18 pjf
 
323
    -- start to tx IP data
324
    ip_tx.data.data_out_valid <= '1';
325
    ip_tx.data.data_out       <= x"c1"; wait until clk = '1';
326
    ip_tx.data.data_out       <= x"c2"; wait until clk = '1';
327
    ip_tx.data.data_out       <= x"c3"; wait until clk = '1';
328
    ip_tx.data.data_out       <= x"c4"; wait until clk = '1';
329
    ip_tx.data.data_out       <= x"c5"; wait until clk = '1';
330
 
331
    ip_tx.data.data_out      <= x"c6";
332
    ip_tx.data.data_out_last <= '1';
333
    wait until clk = '1';
334
 
335
    assert mac_data_out_last = '1' report "T2: mac_datda_out_last not set on last byte";
336
 
337
 
338
    ip_tx.data.data_out_valid <= '0';
339
    ip_tx.data.data_out_last  <= '0';
340
    wait until clk = '1'; wait until clk = '1';
341
    assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be IPTX_RESULT_SENT";
342
    assert mac_tx_req = '0' report "T2: mac_tx_req held on too long after TX";
343
 
344
    mac_tx_granted <= '0';
345 29 pjf
    wait until clk = '1'; wait until clk = '1';
346
 
347 18 pjf
    ------------
348
    -- TEST 3 -- tx test for IP broadcast, should be no arp req
349
    ------------
350
 
351
    report "T3: tx test for IP broadcast, should be no arp req";
352
 
353
    ip_tx.hdr.protocol    <= x"11";
354
    ip_tx.hdr.data_length <= x"0006";
355
    ip_tx.hdr.dst_ip_addr <= x"ffffffff";
356
    ip_tx_start           <= '1';
357
    wait until clk = '1';
358
    ip_tx_start           <= '0'; wait until clk = '1';
359
    arp_req_rslt.got_mac  <= '0';
360
 
361
    assert arp_req_req.lookup_req = '0' report "T3: its trying to do an ARP req tx start";
362
    assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING";
363
 
364
    wait until clk = '1';                -- simulate mac chn access time
365
    mac_tx_granted     <= '1';
366 29 pjf
    wait until clk = '1'; wait until falling_edge(clk);     mac_data_out_ready <= '1';
367 18 pjf
 
368
    assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early";
369
 
370 29 pjf
         -- check data output to MAC layer
371
         if mac_data_out_valid = '0' then
372
                report "T3: waiting for mac_data_out_valid";
373
                wait until mac_data_out_valid = '1';
374
                wait until falling_edge(clk);
375
         end if;
376
         report "T3: got mac_data_out_valid";
377
         assert mac_data_out = x"ff"    report "T3a1: mac_data_out incorrect";  wait for clk_period;
378
         assert mac_data_out = x"ff"    report "T3a2: mac_data_out incorrect";  wait for clk_period;
379
         assert mac_data_out = x"ff"    report "T3a3: mac_data_out incorrect";  wait for clk_period;
380
         assert mac_data_out = x"ff"    report "T3a4: mac_data_out incorrect";  wait for clk_period;
381
         assert mac_data_out = x"ff"    report "T3a5: mac_data_out incorrect";  wait for clk_period;
382
         assert mac_data_out = x"ff"    report "T3a6: mac_data_out incorrect";  wait for clk_period;
383
         assert mac_data_out = x"00"    report "T3b1: mac_data_out incorrect";  wait for clk_period;
384
         assert mac_data_out = x"23"    report "T3b2: mac_data_out incorrect";  wait for clk_period;
385
         assert mac_data_out = x"20"    report "T3b3: mac_data_out incorrect";  wait for clk_period;
386
         assert mac_data_out = x"21"    report "T3b4: mac_data_out incorrect";  wait for clk_period;
387
         assert mac_data_out = x"22"    report "T3b5: mac_data_out incorrect";  wait for clk_period;
388
         assert mac_data_out = x"23"    report "T3b6: mac_data_out incorrect";  wait for clk_period;
389
         assert mac_data_out = x"08"    report "T3c1: mac_data_out incorrect";  wait for clk_period;
390
         assert mac_data_out = x"00"    report "T3c2: mac_data_out incorrect";  wait for clk_period;
391
         assert mac_data_out = x"45"    report "T3d1: mac_data_out incorrect";  wait for clk_period;
392
         assert mac_data_out = x"00"    report "T3d2: mac_data_out incorrect";  wait for clk_period;
393
         assert mac_data_out = x"00"    report "T3d3: mac_data_out incorrect";  wait for clk_period;
394
         assert mac_data_out = x"1a"    report "T3d4: mac_data_out incorrect";  wait for clk_period;
395
         assert mac_data_out = x"00"    report "T3e1: mac_data_out incorrect";  wait for clk_period;
396
         assert mac_data_out = x"00"    report "T3e2: mac_data_out incorrect";  wait for clk_period;
397
         assert mac_data_out = x"00"    report "T3e3: mac_data_out incorrect";  wait for clk_period;
398
         assert mac_data_out = x"00"    report "T3e4: mac_data_out incorrect";  wait for clk_period;
399
         assert mac_data_out = x"80"    report "T3f1: mac_data_out incorrect";  wait for clk_period;
400
         assert mac_data_out = x"11"    report "T3f2: mac_data_out incorrect";  wait for clk_period;
401
         assert mac_data_out = x"75"    report "T3f3: mac_data_out incorrect";  wait for clk_period;
402
         assert mac_data_out = x"22"    report "T3f4: mac_data_out incorrect";  wait for clk_period;
403
 
404
         if ip_tx_data_out_ready = '0' then
405
                wait until ip_tx_data_out_ready = '1';
406
                wait until falling_edge(clk);
407
         end if;
408 18 pjf
 
409
    -- start to tx IP data
410
    ip_tx.data.data_out_valid <= '1';
411
    ip_tx.data.data_out       <= x"c1"; wait until clk = '1';
412
    ip_tx.data.data_out       <= x"c2"; wait until clk = '1';
413
    ip_tx.data.data_out       <= x"c3"; wait until clk = '1';
414
    ip_tx.data.data_out       <= x"c4"; wait until clk = '1';
415
    ip_tx.data.data_out       <= x"c5"; wait until clk = '1';
416
 
417
    ip_tx.data.data_out      <= x"c6";
418
    ip_tx.data.data_out_last <= '1';
419
    wait until clk = '1';
420
 
421
    assert mac_data_out_last = '1' report "T3: mac_datda_out_last not set on last byte";
422
 
423
 
424
    ip_tx.data.data_out_valid <= '0';
425
    ip_tx.data.data_out_last  <= '0';
426
    wait until clk = '1'; wait until clk = '1';
427
    assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be IPTX_RESULT_SENT";
428
    assert mac_tx_req = '0' report "T3: mac_tx_req held on too long after TX";
429
 
430
    mac_tx_granted <= '0';
431
    wait until clk = '1'; wait until clk = '1';
432 29 pjf
 
433
    ------------
434
    -- TEST 4 -- tx test for specific data pattern which gives CKS rollover. use IP broadcast, should be no arp req
435
    ------------
436
 
437
         -- 22:11:05.985469 IP (tos 0x0, ttl 64, id 46647, offset 0, flags [DF], 
438
         -- proto UDP (17), length 39, bad cksum fffe (->fffd)!)
439
    -- 192.168.1.220.999 > 192.168.1.100.37015: [udp sum ok] UDP, length 11
440
    -- 0x0000:  0090 f5c3 2638 0200 0000 0000 0800 4500
441
    -- 0x0010:  0027 b637 4000 4011 fffe c0a8 01dc c0a8
442
    -- 0x0020:  0164 03e7 9097 0013 2196 8105 0100 531c
443
    -- 0x0030:  f000 0000 0000 0000 0000 0000
444
 
445
 report "T4: tx test for cks rollover (IP broadcast, should be no arp req)";
446
 -- TODO fix this up so it sends appropriate data to get cks rollover to show 2nd add required
447
 
448
    our_ip_address            <= x"c0a87a30";  -- set to force cks ovf condition
449
    our_mac_address           <= x"002320212223";
450
    ip_tx.hdr.protocol    <= x"11";
451
    ip_tx.hdr.data_length <= x"0004";
452
    ip_tx.hdr.dst_ip_addr <= x"ffffffff";
453
    ip_tx_start           <= '1';
454
    wait until clk = '1';
455
    ip_tx_start           <= '0'; wait until clk = '1';
456
    arp_req_rslt.got_mac  <= '0';
457 18 pjf
 
458 29 pjf
    assert arp_req_req.lookup_req = '0' report "T4: its trying to do an ARP req tx start";
459
    assert ip_tx_result = IPTX_RESULT_SENDING report "T4: result should be IPTX_RESULT_SENDING";
460
 
461
    wait until clk = '1';                -- simulate mac chn access time
462
    mac_tx_granted     <= '1';
463
    wait until clk = '1'; wait until falling_edge(clk);     mac_data_out_ready <= '1';
464
 
465
    assert ip_tx_data_out_ready = '0' report "T4: IP data out ready asserted too early";
466
 
467
         -- check data output to MAC layer
468
         if mac_data_out_valid = '0' then
469
                report "T4: waiting for mac_data_out_valid";
470
                wait until mac_data_out_valid = '1';
471
                wait until falling_edge(clk);
472
         end if;
473
         report "T4: got mac_data_out_valid";
474
         assert mac_data_out = x"ff"    report "T4a1: mac_data_out incorrect";  wait for clk_period;
475
         assert mac_data_out = x"ff"    report "T4a2: mac_data_out incorrect";  wait for clk_period;
476
         assert mac_data_out = x"ff"    report "T4a3: mac_data_out incorrect";  wait for clk_period;
477
         assert mac_data_out = x"ff"    report "T4a4: mac_data_out incorrect";  wait for clk_period;
478
         assert mac_data_out = x"ff"    report "T4a5: mac_data_out incorrect";  wait for clk_period;
479
         assert mac_data_out = x"ff"    report "T4a6: mac_data_out incorrect";  wait for clk_period;
480
         assert mac_data_out = x"00"    report "T4b1: mac_data_out incorrect";  wait for clk_period;
481
         assert mac_data_out = x"23"    report "T4b2: mac_data_out incorrect";  wait for clk_period;
482
         assert mac_data_out = x"20"    report "T4b3: mac_data_out incorrect";  wait for clk_period;
483
         assert mac_data_out = x"21"    report "T4b4: mac_data_out incorrect";  wait for clk_period;
484
         assert mac_data_out = x"22"    report "T4b5: mac_data_out incorrect";  wait for clk_period;
485
         assert mac_data_out = x"23"    report "T4b6: mac_data_out incorrect";  wait for clk_period;
486
         assert mac_data_out = x"08"    report "T4c1: mac_data_out incorrect";  wait for clk_period;
487
         assert mac_data_out = x"00"    report "T4c2: mac_data_out incorrect";  wait for clk_period;
488
         assert mac_data_out = x"45"    report "T4d1: mac_data_out incorrect";  wait for clk_period;
489
         assert mac_data_out = x"00"    report "T4d2: mac_data_out incorrect";  wait for clk_period;
490
         assert mac_data_out = x"00"    report "T4d3: mac_data_out incorrect";  wait for clk_period;
491
         assert mac_data_out = x"18"    report "T4d4: mac_data_out incorrect";  wait for clk_period;
492
         assert mac_data_out = x"00"    report "T4e1: mac_data_out incorrect";  wait for clk_period;
493
         assert mac_data_out = x"00"    report "T4e2: mac_data_out incorrect";  wait for clk_period;
494
         assert mac_data_out = x"00"    report "T4e3: mac_data_out incorrect";  wait for clk_period;
495
         assert mac_data_out = x"00"    report "T4e4: mac_data_out incorrect";  wait for clk_period;
496
         assert mac_data_out = x"80"    report "T4f1: mac_data_out incorrect";  wait for clk_period;
497
         assert mac_data_out = x"11"    report "T4f2: mac_data_out incorrect";  wait for clk_period;
498
         assert mac_data_out = x"ff"    report "T4f3: mac_data_out incorrect";  wait for clk_period;
499
         assert mac_data_out = x"fc"    report "T4f4: mac_data_out incorrect";  wait for clk_period;
500
 
501
         if ip_tx_data_out_ready = '0' then
502
                wait until ip_tx_data_out_ready = '1';
503
                wait until falling_edge(clk);
504
         end if;
505
 
506
    -- start to tx IP data
507
    ip_tx.data.data_out_valid <= '1';
508
    ip_tx.data.data_out       <= x"c1"; wait until clk = '1';
509
    ip_tx.data.data_out       <= x"c2"; wait until clk = '1';
510
    ip_tx.data.data_out       <= x"c3"; wait until clk = '1';
511
    ip_tx.data.data_out       <= x"c4";
512
    ip_tx.data.data_out_last <= '1';
513
    wait until clk = '1';
514
 
515
    assert mac_data_out_last = '1' report "T4: mac_datda_out_last not set on last byte";
516
 
517
 
518
    ip_tx.data.data_out_valid <= '0';
519
    ip_tx.data.data_out_last  <= '0';
520
    wait until clk = '1'; wait until clk = '1';
521
    assert ip_tx_result = IPTX_RESULT_SENT report "T4: result should be IPTX_RESULT_SENT";
522
    assert mac_tx_req = '0' report "T4: mac_tx_req held on too long after TX";
523
 
524
    mac_tx_granted <= '0';
525
    wait until clk = '1'; wait until clk = '1';
526
 
527 18 pjf
    report "--- end of tests ---";
528
 
529
    wait;
530
  end process;
531
 
532
end;

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.