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[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [UDP_TX_tb.vhd] - Blame information for rev 8

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1 2 pjf
--------------------------------------------------------------------------------
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-- Company: 
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-- Engineer:
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--
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-- Create Date:   18:43:49 06/10/2011
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-- Design Name:   
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-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_TX_tb.vhd
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-- Project Name:  ip1
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-- Target Device:  
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-- Tool versions:  
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-- Description:   
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-- 
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-- VHDL Test Bench Created by ISE for module: UDP_TX
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-- 
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-- Dependencies:
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-- 
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes: 
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation 
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-- simulation model.
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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ENTITY UDP_TX_tb IS
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END UDP_TX_tb;
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ARCHITECTURE behavior OF UDP_TX_tb IS
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    -- Component Declaration for the Unit Under Test (UUT)
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    COMPONENT UDP_TX
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    PORT(
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                        -- UDP Layer signals
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                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
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                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
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                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
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                        -- system signals
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                        clk                                             : in  STD_LOGIC;                                                        -- same clock used to clock mac data and ip data
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                        reset                                   : in  STD_LOGIC;
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                        -- IP layer TX signals
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                        ip_tx_start                             : out std_logic;
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                        ip_tx                                           : out ipv4_tx_type;                                                     -- IP tx cxns
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                        ip_tx_result                    : in std_logic_vector (1 downto 0);              -- tx status (changes during transmission)
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                        ip_tx_data_out_ready    : in std_logic                                                                  -- indicates IP TX is ready to take data
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        );
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    END COMPONENT;
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   --Inputs
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   signal udp_tx_start : std_logic := '0';
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   signal clk : std_logic := '0';
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   signal reset : std_logic := '0';
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   signal udp_txi : udp_tx_type;
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        signal ip_tx_result                     : std_logic_vector (1 downto 0);         -- tx status (changes during transmission)
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        signal ip_tx_data_out_ready : std_logic;                                                                -- indicates IP TX is ready to take data
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        --Outputs
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   signal ip_tx_start : std_logic := '0';
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   signal ip_tx : ipv4_tx_type;
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   signal udp_tx_result : std_logic_vector (1 downto 0);
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   signal udp_tx_data_out_ready : std_logic;
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   -- Clock period definitions
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   constant clk_period : time := 8 ns;
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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   uut: UDP_TX PORT MAP (
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          udp_tx_start => udp_tx_start,
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          udp_txi => udp_txi,
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          udp_tx_result => udp_tx_result,
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          udp_tx_data_out_ready => udp_tx_data_out_ready,
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          clk => clk,
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          reset => reset,
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          ip_tx_start => ip_tx_start,
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          ip_tx => ip_tx,
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          ip_tx_result => ip_tx_result,
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          ip_tx_data_out_ready => ip_tx_data_out_ready
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        );
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   -- Clock process definitions
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   clk_process :process
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   begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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   end process;
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   -- Stimulus process
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   stim_proc: process
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   begin
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      -- hold reset state for 100 ns.
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      wait for 100 ns;
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                udp_tx_start <= '0';
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                udp_txi.hdr.dst_ip_addr <= (others => '0');
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                udp_txi.hdr.dst_port <= (others => '0');
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                udp_txi.hdr.src_port <= (others => '0');
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                udp_txi.hdr.data_length <= (others => '0');
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                udp_txi.hdr.checksum <= (others => '0');
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      udp_txi.data.data_out_last <= '0';
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                reset <= '1';
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      wait for clk_period*10;
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                reset <= '0';
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      wait for clk_period*5;
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                -- check reset conditions
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                assert ip_tx_start = '0'                                                 report "ip_tx_start not initialised correctly on reset";
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                assert ip_tx.data.data_out_valid = '0'   report "ip_tx.data.data_out_valid not initialised correctly on reset";
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                assert ip_tx.data.data_out_last = '0'            report "ip_tx.data.data_out_last not initialised correctly on reset";
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                assert udp_tx_result = UDPTX_RESULT_NONE        report "udp_tx_result not initialised correctly on reset";
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      -- insert stimulus here 
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      wait for clk_period*5;
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                ------------
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                -- TEST 1 -- basic functional tx test 
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                ------------
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                report "T1: basic functional tx test - send 56, 57, 58 to port 8532";
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                udp_txi.hdr.dst_ip_addr <= x"c0123478";
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                udp_txi.hdr.dst_port <= x"1467";
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                udp_txi.hdr.src_port <= x"8532";
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                udp_txi.hdr.data_length <= x"0003";
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                udp_tx_start <= '1';
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                ip_tx_data_out_ready <= '1';            -- IP layer can accept data
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                wait for clk_period;
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                udp_tx_start <= '0'; wait for clk_period;
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                ip_tx_result <= IPTX_RESULT_NONE;
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                assert udp_tx_result = UDPTX_RESULT_SENDING             report "T1: result should be UDPTX_RESULT_SENDING";
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                wait until udp_tx_data_out_ready = '1';
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                -- start to tx IP data
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                udp_txi.data.data_out_valid <= '1';
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                udp_txi.data.data_out <= x"56"; wait for clk_period;
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                udp_txi.data.data_out <= x"57"; wait for clk_period;
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                udp_txi.data.data_out <= x"58";
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                udp_txi.data.data_out_last <= '1';
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                wait for clk_period;
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                assert ip_tx.data.data_out_last = '1'                   report "T1: ip_tx.datda_out_last not set on last byte";
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                udp_txi.data.data_out_valid <= '0';
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                udp_txi.data.data_out_last <= '0';
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                wait for clk_period*2;
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                ip_tx_result <= IPTX_RESULT_SENT;
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                assert udp_tx_result = UDPTX_RESULT_SENT        report "T1: result should be UDPTX_RESULT_SENT";
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                wait for clk_period*2;
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                ------------
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                -- TEST 2 -- 2nd pkt
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                ------------
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                report "T2: send a second pkt - 56,57,58,59 to port 8532";
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                udp_txi.hdr.dst_ip_addr <= x"c0123475";
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                udp_txi.hdr.dst_port <= x"1467";
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                udp_txi.hdr.src_port <= x"8532";
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                udp_txi.hdr.data_length <= x"0005";
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                udp_tx_start <= '1';
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                ip_tx_data_out_ready <= '1';            -- IP layer can accept data
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                wait for clk_period;
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                udp_tx_start <= '0'; wait for clk_period;
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                assert udp_tx_result = UDPTX_RESULT_SENDING             report "T1: result should be UDPTX_RESULT_SENDING";
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                wait until udp_tx_data_out_ready = '1';
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                -- start to tx IP data
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                udp_txi.data.data_out_valid <= '1';
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                udp_txi.data.data_out <= x"56"; wait for clk_period;
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                udp_txi.data.data_out <= x"57"; wait for clk_period;
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                udp_txi.data.data_out <= x"58"; wait for clk_period;
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                udp_txi.data.data_out <= x"59"; wait for clk_period;
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                udp_txi.data.data_out <= x"5a";
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                udp_txi.data.data_out_last <= '1';
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                wait for clk_period;
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                assert ip_tx.data.data_out_last = '1'                   report "T1: ip_tx.datda_out_last not set on last byte";
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                udp_txi.data.data_out_valid <= '0';
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                udp_txi.data.data_out_last <= '0';
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                wait for clk_period*2;
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                assert udp_tx_result = UDPTX_RESULT_SENT        report "T1: result should be UDPTX_RESULT_SENT";
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                wait for clk_period*2;
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                report "--- end of tests ---";
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      wait;
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   end process;
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END;

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