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[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [UDP_complete_nomac_tb.vhd] - Blame information for rev 6

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1 2 pjf
--------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer:
4
--
5
-- Create Date:   09:57:01 06/13/2011
6
-- Design Name:   
7
-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/udp1/UDP_complete_nomac_tb.vhd
8
-- Project Name:  udp1
9
-- Target Device:  
10
-- Tool versions:  
11
-- Description:   
12
-- 
13
-- VHDL Test Bench Created by ISE for module: UDP_Complete_nomac
14
-- 
15
-- Dependencies:
16
-- 
17
-- Revision:
18
-- Revision 0.01 - File Created
19 6 pjf
-- Revision 0.02 - Added test for IP broadcast tx
20 2 pjf
-- Additional Comments:
21
--
22
-- Notes: 
23
-- This testbench has been automatically generated using types std_logic and
24
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
25
-- that these types always be used for the top-level I/O of a design in order
26
-- to guarantee that the testbench will bind correctly to the post-implementation 
27
-- simulation model.
28
--------------------------------------------------------------------------------
29
library IEEE;
30
use IEEE.STD_LOGIC_1164.ALL;
31
use IEEE.NUMERIC_STD.ALL;
32
use work.axi.all;
33
use work.ipv4_types.all;
34
use work.arp_types.all;
35
 
36
ENTITY UDP_complete_nomac_tb IS
37
END UDP_complete_nomac_tb;
38
 
39
ARCHITECTURE behavior OF UDP_complete_nomac_tb IS
40
 
41
    -- Component Declaration for the Unit Under Test (UUT)
42
 
43
    COMPONENT UDP_Complete_nomac
44
    PORT(
45
                        -- UDP TX signals
46
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
47
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
48
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
49
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
50
                        -- UDP RX signals
51
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
52
                        udp_rxo                                 : out udp_rx_type;
53
                        -- IP RX signals
54
                        ip_rx_hdr                               : out ipv4_rx_header_type;
55
                        -- system signals
56
                        rx_clk                                  : in  STD_LOGIC;
57
                        tx_clk                                  : in  STD_LOGIC;
58
                        reset                                   : in  STD_LOGIC;
59
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
60
                        our_mac_address                 : in std_logic_vector (47 downto 0);
61
                        -- status signals
62
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
63
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
64
                        -- MAC Transmitter
65
                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
66
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
67
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
68 4 pjf
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
69 2 pjf
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
70
                        -- MAC Receiver
71
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
72
                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
73
                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
74
                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
75
                        );
76
    END COMPONENT;
77
 
78
 
79
 
80
        type state_type is (IDLE, DATA_OUT);
81
        type count_mode_type is (RST, INCR, HOLD);
82
        type set_clr_type is (SET, CLR, HOLD);
83
 
84
 
85
   --Inputs
86
   signal udp_tx_start_int : std_logic := '0';
87
   signal udp_tx_int : udp_tx_type;
88
   signal clk_int : std_logic := '0';
89
   signal reset : std_logic := '0';
90
   signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
91
   signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
92
   signal mac_tx_tready : std_logic := '0';
93
   signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
94
   signal mac_rx_tvalid : std_logic := '0';
95
   signal mac_rx_tlast : std_logic := '0';
96
 
97
        --Outputs
98
   signal udp_rx_start_int : std_logic;
99
   signal udp_rx_int : udp_rx_type;
100
   signal ip_rx_hdr : ipv4_rx_header_type;
101
        signal udp_tx_result    : std_logic_vector (1 downto 0);
102
        signal udp_tx_data_out_ready_int: std_logic;
103
 
104
   signal arp_pkt_count : std_logic_vector(7 downto 0);
105
   signal ip_pkt_count : std_logic_vector(7 downto 0);
106
   signal mac_tx_tdata : std_logic_vector(7 downto 0);
107
   signal mac_tx_tvalid : std_logic;
108 4 pjf
   signal mac_tx_tfirst : std_logic;
109 2 pjf
   signal mac_tx_tlast : std_logic;
110
   signal mac_rx_tready : std_logic;
111
 
112
        signal pbtx_led : std_logic;
113
        signal pbtx : std_logic := '0';
114
 
115
        -- state signals
116
        signal state                    : state_type;
117
        signal count                    : unsigned (7 downto 0);
118
        signal tx_hdr                   : udp_tx_header_type;
119
        signal tx_start_reg     : std_logic;
120
        signal tx_started_reg : std_logic;
121
        signal tx_fin_reg               : std_logic;
122
 
123
 
124
        -- control signals
125
        signal next_state               : state_type;
126
        signal set_state                : std_logic;
127
        signal set_count                : count_mode_type;
128
        signal set_hdr                  : std_logic;
129
        signal set_tx_start     : set_clr_type;
130
        signal set_last         : std_logic;
131
        signal set_tx_started : set_clr_type;
132
        signal set_tx_fin       : set_clr_type;
133
 
134
 
135
 
136
   -- Clock period definitions
137
   constant clk_period : time := 8 ns;
138
 
139
BEGIN
140
 
141
        -- Instantiate the Unit Under Test (UUT)
142
   uut: UDP_Complete_nomac PORT MAP (
143
          udp_tx_start => udp_tx_start_int,
144
          udp_txi => udp_tx_int,
145
          udp_tx_result => udp_tx_result,
146
          udp_tx_data_out_ready => udp_tx_data_out_ready_int,
147
          udp_rx_start => udp_rx_start_int,
148
          udp_rxo => udp_rx_int,
149
          ip_rx_hdr => ip_rx_hdr,
150
          rx_clk => clk_int,
151
                         tx_clk => clk_int,
152
          reset => reset,
153
          our_ip_address => our_ip_address,
154
          our_mac_address => our_mac_address,
155
          arp_pkt_count => arp_pkt_count,
156
          ip_pkt_count => ip_pkt_count,
157
          mac_tx_tdata => mac_tx_tdata,
158
          mac_tx_tvalid => mac_tx_tvalid,
159
          mac_tx_tready => mac_tx_tready,
160 4 pjf
          mac_tx_tfirst => mac_tx_tfirst,
161 2 pjf
          mac_tx_tlast => mac_tx_tlast,
162
          mac_rx_tdata => mac_rx_tdata,
163
          mac_rx_tvalid => mac_rx_tvalid,
164
          mac_rx_tready => mac_rx_tready,
165
          mac_rx_tlast => mac_rx_tlast
166
        );
167
 
168
   -- Clock process definitions
169
   clk_process :process
170
   begin
171
                clk_int <= '0';
172
                wait for clk_period/2;
173
                clk_int <= '1';
174
                wait for clk_period/2;
175
   end process;
176
 
177
 
178
   -- Stimulus process
179
   stim_proc: process
180
   begin
181
      -- hold reset state for 100 ns.
182
      wait for 100 ns;
183
 
184
                our_ip_address <= x"c0a80509";          -- 192.168.5.9
185
                our_mac_address <= x"002320212223";
186
      mac_tx_tready <= '0';
187
 
188
                reset <= '1';
189
      wait for clk_period*10;
190
                reset <= '0';
191
      wait for clk_period*5;
192
 
193
                -- check reset conditions
194
                assert udp_tx_result = UDPTX_RESULT_NONE                report "udp_tx_result not initialised correctly on reset";
195
                assert udp_tx_data_out_ready_int = '0'           report "ip_udp_txitx.data.data_out_ready not initialised correctly on reset";
196
                assert mac_tx_tvalid = '0'                                               report "mac_tx_tvalid not initialised correctly on reset";
197
                assert mac_tx_tlast = '0'                                                        report "mac_tx_tlast not initialised correctly on reset";
198
                assert arp_pkt_count = x"00"                                            report "arp_pkt_count not initialised correctly on reset";
199
                assert ip_pkt_count = x"00"                                             report "ip_pkt_count not initialised correctly on reset";
200
                assert udp_rx_start_int = '0'                                                    report "udp_rx_start not initialised correctly on reset";
201
                assert udp_rx_int.hdr.is_valid = '0'                             report "udp_rx_int.hdr.is_valid not initialised correctly on reset";
202
                assert udp_rx_int.hdr.data_length = x"0000"             report "udp_rx_int.hdr.data_length not initialised correctly on reset";
203
                assert udp_rx_int.hdr.src_ip_addr = x"00000000" report "udp_rx_int.hdr.src_ip_addr not initialised correctly on reset";
204
                assert udp_rx_int.hdr.src_port = x"0000"                        report "udp_rx_int.hdr.src_port not initialised correctly on reset";
205
                assert udp_rx_int.hdr.dst_port = x"0000"                        report "udp_rx_int.hdr.dst_port not initialised correctly on reset";
206
                assert udp_rx_int.data.data_in = x"00"                          report "udp_rx_start.data.data_in not initialised correctly on reset";
207
                assert udp_rx_int.data.data_in_valid = '0'               report "udp_rx_start.data.data_in_valid not initialised correctly on reset";
208
                assert udp_rx_int.data.data_in_last = '0'                        report "udp_rx_start.data.data_in_last not initialised correctly on reset";
209
                assert ip_rx_hdr.is_valid = '0'                                  report "ip_rx_hdr.is_valid not initialised correctly on reset";
210
                assert ip_rx_hdr.protocol = x"00"                               report "ip_rx_hdr.protocol not initialised correctly on reset";
211
                assert ip_rx_hdr.data_length = x"0000"                  report "ip_rx_hdr.data_length not initialised correctly on reset";
212
                assert ip_rx_hdr.src_ip_addr = x"00000000"      report "ip_rx_hdr.src_ip_addr not initialised correctly on reset";
213
                assert ip_rx_hdr.num_frame_errors = x"00"               report "ip_rx_hdr.num_frame_errors not initialised correctly on reset";
214
 
215
 
216
      -- insert stimulus here 
217
 
218
                ------------
219
                -- TEST 1 -- send ARP request
220
                ------------
221
 
222
                report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
223
 
224
      mac_tx_tready <= '1';
225
 
226
                mac_rx_tvalid <= '1';
227
                -- dst MAC (bc)
228
                mac_rx_tdata <= x"ff"; wait for clk_period;
229
                mac_rx_tdata <= x"ff"; wait for clk_period;
230
                mac_rx_tdata <= x"ff"; wait for clk_period;
231
                mac_rx_tdata <= x"ff"; wait for clk_period;
232
                mac_rx_tdata <= x"ff"; wait for clk_period;
233
                mac_rx_tdata <= x"ff"; wait for clk_period;
234
                -- src MAC
235
                mac_rx_tdata <= x"00"; wait for clk_period;
236
                mac_rx_tdata <= x"23"; wait for clk_period;
237
                mac_rx_tdata <= x"18"; wait for clk_period;
238
                mac_rx_tdata <= x"29"; wait for clk_period;
239
                mac_rx_tdata <= x"26"; wait for clk_period;
240
                mac_rx_tdata <= x"7c"; wait for clk_period;
241
                -- type
242
                mac_rx_tdata <= x"08"; wait for clk_period;
243
                mac_rx_tdata <= x"06"; wait for clk_period;
244
                -- HW type
245
                mac_rx_tdata <= x"00"; wait for clk_period;
246
                mac_rx_tdata <= x"01"; wait for clk_period;
247
                -- Protocol type
248
                mac_rx_tdata <= x"08"; wait for clk_period;
249
                mac_rx_tdata <= x"00"; wait for clk_period;
250
                -- HW size
251
                mac_rx_tdata <= x"06"; wait for clk_period;
252
                -- protocol size
253
                mac_rx_tdata <= x"04"; wait for clk_period;
254
                -- Opcode
255
                mac_rx_tdata <= x"00"; wait for clk_period;
256
                mac_rx_tdata <= x"01"; wait for clk_period;
257
                -- Sender MAC
258
                mac_rx_tdata <= x"00"; wait for clk_period;
259
                mac_rx_tdata <= x"23"; wait for clk_period;
260
                mac_rx_tdata <= x"18"; wait for clk_period;
261
                mac_rx_tdata <= x"29"; wait for clk_period;
262
                mac_rx_tdata <= x"26"; wait for clk_period;
263
                mac_rx_tdata <= x"7c"; wait for clk_period;
264
                -- Sender IP
265
                mac_rx_tdata <= x"c0"; wait for clk_period;
266
                mac_rx_tdata <= x"a8"; wait for clk_period;
267
                mac_rx_tdata <= x"05"; wait for clk_period;
268
                mac_rx_tdata <= x"01"; wait for clk_period;
269
                -- Target MAC
270
                mac_rx_tdata <= x"00"; wait for clk_period;
271
                mac_rx_tdata <= x"00"; wait for clk_period;
272
                mac_rx_tdata <= x"00"; wait for clk_period;
273
                mac_rx_tdata <= x"00"; wait for clk_period;
274
                mac_rx_tdata <= x"00"; wait for clk_period;
275
                mac_rx_tdata <= x"00"; wait for clk_period;
276
                -- Target IP
277
                mac_rx_tdata <= x"c0"; wait for clk_period;
278
                mac_rx_tdata <= x"a8"; wait for clk_period;
279
                mac_rx_tdata <= x"05"; wait for clk_period;
280
                mac_rx_tdata <= x"09"; wait for clk_period;
281
                mac_rx_tdata <= x"00"; wait for clk_period;
282
                mac_rx_tdata <= x"00"; wait for clk_period;
283
                mac_rx_tdata <= x"00"; wait for clk_period;
284
                mac_rx_tlast <= '1';
285
                mac_rx_tdata <= x"00"; wait for clk_period;
286
                mac_rx_tlast <= '0';
287
                mac_rx_tvalid <= '0';
288
 
289
                -- check we got the ARP pkt
290
                assert arp_pkt_count = x"01"                                            report "T1: arp_pkt_count wrong value";
291
                assert ip_pkt_count = x"00"                                             report "T1: ip_pkt_count wrong value";
292
                assert udp_tx_result = UDPTX_RESULT_NONE                report "T1: udp_tx_result wrong value";
293
                assert udp_tx_data_out_ready_int = '0'           report "T1: ip_udp_txitx.data.data_out_ready wrong value";
294
                assert udp_rx_start_int = '0'                                                    report "T1: udp_rx_start wrong value";
295
                assert udp_rx_int.hdr.is_valid = '0'                             report "T1: udp_rx_int.hdr.is_valid wrong value";
296
                assert ip_rx_hdr.is_valid = '0'                                  report "T1: ip_rx_hdr.is_valid wrong value";
297
 
298
                -- check we tx a response
299
 
300
                wait for clk_period*25;
301
                assert mac_tx_tvalid = '1'                                                      report "T1: not transmitting a response";
302
                wait for clk_period*25;
303
                assert mac_tx_tvalid = '0'                                                       report "T1: tx held on for too long";
304
 
305
                ------------
306
                -- TEST 2 -- send UDP pkt (same as sample from Java program
307
                ------------
308
 
309
                report "T2: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
310
 
311
                mac_rx_tvalid <= '1';
312
                -- dst MAC (bc)
313
                mac_rx_tdata <= x"00"; wait for clk_period;
314
                mac_rx_tdata <= x"23"; wait for clk_period;
315
                mac_rx_tdata <= x"20"; wait for clk_period;
316
                mac_rx_tdata <= x"21"; wait for clk_period;
317
                mac_rx_tdata <= x"22"; wait for clk_period;
318
                mac_rx_tdata <= x"23"; wait for clk_period;
319
                -- src MAC
320
                mac_rx_tdata <= x"00"; wait for clk_period;
321
                mac_rx_tdata <= x"23"; wait for clk_period;
322
                mac_rx_tdata <= x"18"; wait for clk_period;
323
                mac_rx_tdata <= x"29"; wait for clk_period;
324
                mac_rx_tdata <= x"26"; wait for clk_period;
325
                mac_rx_tdata <= x"7c"; wait for clk_period;
326
                -- type
327
                mac_rx_tdata <= x"08"; wait for clk_period;             -- IP pkt
328
                mac_rx_tdata <= x"00"; wait for clk_period;
329
                -- ver & HL / service type
330
                mac_rx_tdata <= x"45"; wait for clk_period;
331
                mac_rx_tdata <= x"00"; wait for clk_period;
332
                -- total len
333
                mac_rx_tdata <= x"00"; wait for clk_period;
334
                mac_rx_tdata <= x"21"; wait for clk_period;
335
                -- ID
336
                mac_rx_tdata <= x"00"; wait for clk_period;
337
                mac_rx_tdata <= x"7a"; wait for clk_period;
338
                -- flags & frag
339
                mac_rx_tdata <= x"00"; wait for clk_period;
340
                mac_rx_tdata <= x"00"; wait for clk_period;
341
                -- TTL
342
                mac_rx_tdata <= x"80"; wait for clk_period;
343
                -- Protocol
344
                mac_rx_tdata <= x"11"; wait for clk_period;
345
                -- Header CKS
346
                mac_rx_tdata <= x"00"; wait for clk_period;
347
                mac_rx_tdata <= x"00"; wait for clk_period;
348
                -- SRC IP
349
                mac_rx_tdata <= x"c0"; wait for clk_period;
350
                mac_rx_tdata <= x"a8"; wait for clk_period;
351
                mac_rx_tdata <= x"05"; wait for clk_period;
352
                mac_rx_tdata <= x"01"; wait for clk_period;
353
                -- DST IP
354
                mac_rx_tdata <= x"c0"; wait for clk_period;
355
                mac_rx_tdata <= x"a8"; wait for clk_period;
356
                mac_rx_tdata <= x"05"; wait for clk_period;
357
                mac_rx_tdata <= x"09"; wait for clk_period;
358
                -- SRC port
359
                mac_rx_tdata <= x"f4"; wait for clk_period;
360
                mac_rx_tdata <= x"9a"; wait for clk_period;
361
                -- DST port
362
                mac_rx_tdata <= x"26"; wait for clk_period;
363
                mac_rx_tdata <= x"94"; wait for clk_period;
364
                -- length
365
                mac_rx_tdata <= x"00"; wait for clk_period;
366
                mac_rx_tdata <= x"0d"; wait for clk_period;
367
                -- cks
368
                mac_rx_tdata <= x"8b"; wait for clk_period;
369
                mac_rx_tdata <= x"79"; wait for clk_period;
370
                -- user data
371
                mac_rx_tdata <= x"68"; wait for clk_period;
372
 
373
                -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
374
                assert udp_rx_int.hdr.is_valid = '1'                            report "T2: udp_rx_int.hdr.is_valid not set";
375
                assert udp_rx_int.hdr.data_length = x"0005"             report "T2: udp_rx_int.hdr.data_length not set correctly";
376
                assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rx_int.hdr.src_ip_addr not set correctly";
377
                assert udp_rx_int.hdr.src_port = x"f49a"                        report "T2: udp_rx_int.hdr.src_port not set correctly";
378
                assert udp_rx_int.hdr.dst_port = x"2694"                        report "T2: udp_rx_int.hdr.dst_port not set correctly";
379
 
380
                assert udp_rx_start_int = '1'                                                   report "T2: udp_rx_start not set";
381
                assert udp_rx_int.data.data_in_valid = '1'              report "T2: udp_rx_int.data.data_in_valid not set";
382
 
383
                assert ip_rx_hdr.is_valid = '1'                                 report "T2: ip_rx_hdr.is_valid not set";
384
                assert ip_rx_hdr.protocol = x"11"                               report "T2: ip_rx_hdr.protocol not set correctly";
385
                assert ip_rx_hdr.src_ip_addr = x"c0a80501"      report "T2: ip_rx.hdr.src_ip_addr not set correctly";
386
                assert ip_rx_hdr.num_frame_errors = x"00"       report "T2: ip_rx.hdr.num_frame_errors not set correctly";
387
                assert ip_rx_hdr.last_error_code = x"0"          report "T2: ip_rx.hdr.last_error_code not set correctly";
388
 
389
                -- put the rest of the user data
390
                mac_rx_tdata <= x"65"; wait for clk_period;
391
                mac_rx_tdata <= x"6c"; wait for clk_period;
392
                mac_rx_tdata <= x"6c"; wait for clk_period;
393
                mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
394
 
395
                assert udp_rx_int.data.data_in_last = '1'                       report "T2: udp_rx_int.data.data_in_last not set";
396
 
397
                mac_rx_tdata <= x"00";
398
                mac_rx_tlast <= '0';
399
                mac_rx_tvalid <= '0';
400
                wait for clk_period;
401
 
402
                assert udp_rx_int.data.data_in_valid = '0'               report "T2: udp_rx_int.data.data_in_valid not cleared";
403
                assert udp_rx_int.data.data_in_last = '0'                        report "T2: udp_rx_int.data.data_in_last not cleared";
404
                assert udp_rx_start_int = '0'                                                    report "T2: udp_rx_start not cleared";
405
                assert ip_rx_hdr.num_frame_errors = x"00"               report "T2: ip_rx_hdr.num_frame_errors non zero at end of test";
406
                assert ip_rx_hdr.last_error_code = x"0"          report "T2: ip_rx_hdr.last_error_code indicates error at end of test";
407
                assert ip_pkt_count = x"01"                                             report "T2: ip pkt cnt incorrect";
408
 
409
                wait for clk_period*20;
410
 
411
                ------------
412
                -- TEST 3 -- send UDP pkt again (same as sample from Java program
413
                ------------
414
 
415
                report "T3: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
416
 
417
                mac_rx_tvalid <= '1';
418
                -- dst MAC (bc)
419
                mac_rx_tdata <= x"00"; wait for clk_period;
420
                mac_rx_tdata <= x"23"; wait for clk_period;
421
                mac_rx_tdata <= x"20"; wait for clk_period;
422
                mac_rx_tdata <= x"21"; wait for clk_period;
423
                mac_rx_tdata <= x"22"; wait for clk_period;
424
                mac_rx_tdata <= x"23"; wait for clk_period;
425
                -- src MAC
426
                mac_rx_tdata <= x"00"; wait for clk_period;
427
                mac_rx_tdata <= x"23"; wait for clk_period;
428
                mac_rx_tdata <= x"18"; wait for clk_period;
429
                mac_rx_tdata <= x"29"; wait for clk_period;
430
                mac_rx_tdata <= x"26"; wait for clk_period;
431
                mac_rx_tdata <= x"7c"; wait for clk_period;
432
                -- type
433
                mac_rx_tdata <= x"08"; wait for clk_period;             -- IP pkt
434
                mac_rx_tdata <= x"00"; wait for clk_period;
435
                -- ver & HL / service type
436
                mac_rx_tdata <= x"45"; wait for clk_period;
437
                mac_rx_tdata <= x"00"; wait for clk_period;
438
                -- total len
439
                mac_rx_tdata <= x"00"; wait for clk_period;
440
                mac_rx_tdata <= x"21"; wait for clk_period;
441
                -- ID
442
                mac_rx_tdata <= x"00"; wait for clk_period;
443
                mac_rx_tdata <= x"7a"; wait for clk_period;
444
                -- flags & frag
445
                mac_rx_tdata <= x"00"; wait for clk_period;
446
                mac_rx_tdata <= x"00"; wait for clk_period;
447
                -- TTL
448
                mac_rx_tdata <= x"80"; wait for clk_period;
449
                -- Protocol
450
                mac_rx_tdata <= x"11"; wait for clk_period;
451
                -- Header CKS
452
                mac_rx_tdata <= x"00"; wait for clk_period;
453
                mac_rx_tdata <= x"00"; wait for clk_period;
454
                -- SRC IP
455
                mac_rx_tdata <= x"c0"; wait for clk_period;
456
                mac_rx_tdata <= x"a8"; wait for clk_period;
457
                mac_rx_tdata <= x"05"; wait for clk_period;
458
                mac_rx_tdata <= x"01"; wait for clk_period;
459
                -- DST IP
460
                mac_rx_tdata <= x"c0"; wait for clk_period;
461
                mac_rx_tdata <= x"a8"; wait for clk_period;
462
                mac_rx_tdata <= x"05"; wait for clk_period;
463
                mac_rx_tdata <= x"09"; wait for clk_period;
464
                -- SRC port
465
                mac_rx_tdata <= x"f4"; wait for clk_period;
466
                mac_rx_tdata <= x"9a"; wait for clk_period;
467
                -- DST port
468
                mac_rx_tdata <= x"26"; wait for clk_period;
469
                mac_rx_tdata <= x"94"; wait for clk_period;
470
                -- length
471
                mac_rx_tdata <= x"00"; wait for clk_period;
472
                mac_rx_tdata <= x"0d"; wait for clk_period;
473
                -- cks
474
                mac_rx_tdata <= x"8b"; wait for clk_period;
475
                mac_rx_tdata <= x"79"; wait for clk_period;
476
                -- user data
477
                mac_rx_tdata <= x"68"; wait for clk_period;
478
 
479
                -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
480
                assert udp_rx_int.hdr.is_valid = '1'                            report "T3: udp_rx_int.hdr.is_valid not set";
481
                assert udp_rx_int.hdr.data_length = x"0005"             report "T3: udp_rx_int.hdr.data_length not set correctly";
482
                assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T3: udp_rx_int.hdr.src_ip_addr not set correctly";
483
                assert udp_rx_int.hdr.src_port = x"f49a"                        report "T3: udp_rx_int.hdr.src_port not set correctly";
484
                assert udp_rx_int.hdr.dst_port = x"2694"                        report "T3: udp_rx_int.hdr.dst_port not set correctly";
485
 
486
                assert udp_rx_start_int = '1'                                                   report "T3: udp_rx_start not set";
487
                assert udp_rx_int.data.data_in_valid = '1'              report "T3: udp_rx_int.data.data_in_valid not set";
488
 
489
                assert ip_rx_hdr.is_valid = '1'                                 report "T3: ip_rx_hdr.is_valid not set";
490
                assert ip_rx_hdr.protocol = x"11"                               report "T3: ip_rx_hdr.protocol not set correctly";
491
                assert ip_rx_hdr.src_ip_addr = x"c0a80501"      report "T3: ip_rx.hdr.src_ip_addr not set correctly";
492
                assert ip_rx_hdr.num_frame_errors = x"00"       report "T3: ip_rx.hdr.num_frame_errors not set correctly";
493
                assert ip_rx_hdr.last_error_code = x"0"          report "T3: ip_rx.hdr.last_error_code not set correctly";
494
 
495
                -- put the rest of the user data
496
                mac_rx_tdata <= x"65"; wait for clk_period;
497
                mac_rx_tdata <= x"6c"; wait for clk_period;
498
                mac_rx_tdata <= x"6c"; wait for clk_period;
499
                mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
500
 
501
                assert udp_rx_int.data.data_in_last = '1'                       report "T3: udp_rx_int.data.data_in_last not set";
502
 
503
                mac_rx_tdata <= x"00";
504
                mac_rx_tlast <= '0';
505
                mac_rx_tvalid <= '0';
506
                wait for clk_period;
507
 
508
                assert udp_rx_int.data.data_in_valid = '0'               report "T3: udp_rx_int.data.data_in_valid not cleared";
509
                assert udp_rx_int.data.data_in_last = '0'                        report "T3: udp_rx_int.data.data_in_last not cleared";
510
                assert udp_rx_start_int = '0'                                                    report "T3: udp_rx_start not cleared";
511
                assert ip_rx_hdr.num_frame_errors = x"00"               report "T3: ip_rx_hdr.num_frame_errors non zero at end of test";
512
                assert ip_rx_hdr.last_error_code = x"0"          report "T3: ip_rx_hdr.last_error_code indicates error at end of test";
513
                assert ip_pkt_count = x"02"                                             report "T3: ip pkt cnt incorrect";
514
 
515 6 pjf
 
516
 
517
 
518
 
519
                ------------
520
                -- TEST 4 -- send UDP pkt with src=bc addr to force a broadcast tx in reply
521
                ------------
522
 
523
                report "T4: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
524
 
525
                mac_rx_tvalid <= '1';
526
                -- dst MAC (bc)
527
                mac_rx_tdata <= x"00"; wait for clk_period;
528
                mac_rx_tdata <= x"23"; wait for clk_period;
529
                mac_rx_tdata <= x"20"; wait for clk_period;
530
                mac_rx_tdata <= x"21"; wait for clk_period;
531
                mac_rx_tdata <= x"22"; wait for clk_period;
532
                mac_rx_tdata <= x"23"; wait for clk_period;
533
                -- src MAC
534
                mac_rx_tdata <= x"00"; wait for clk_period;
535
                mac_rx_tdata <= x"23"; wait for clk_period;
536
                mac_rx_tdata <= x"18"; wait for clk_period;
537
                mac_rx_tdata <= x"29"; wait for clk_period;
538
                mac_rx_tdata <= x"26"; wait for clk_period;
539
                mac_rx_tdata <= x"7c"; wait for clk_period;
540
                -- type
541
                mac_rx_tdata <= x"08"; wait for clk_period;             -- IP pkt
542
                mac_rx_tdata <= x"00"; wait for clk_period;
543
                -- ver & HL / service type
544
                mac_rx_tdata <= x"45"; wait for clk_period;
545
                mac_rx_tdata <= x"00"; wait for clk_period;
546
                -- total len
547
                mac_rx_tdata <= x"00"; wait for clk_period;
548
                mac_rx_tdata <= x"21"; wait for clk_period;
549
                -- ID
550
                mac_rx_tdata <= x"00"; wait for clk_period;
551
                mac_rx_tdata <= x"7a"; wait for clk_period;
552
                -- flags & frag
553
                mac_rx_tdata <= x"00"; wait for clk_period;
554
                mac_rx_tdata <= x"00"; wait for clk_period;
555
                -- TTL
556
                mac_rx_tdata <= x"80"; wait for clk_period;
557
                -- Protocol
558
                mac_rx_tdata <= x"11"; wait for clk_period;
559
                -- Header CKS
560
                mac_rx_tdata <= x"00"; wait for clk_period;
561
                mac_rx_tdata <= x"00"; wait for clk_period;
562
                -- SRC IP
563
                mac_rx_tdata <= x"ff"; wait for clk_period;
564
                mac_rx_tdata <= x"ff"; wait for clk_period;
565
                mac_rx_tdata <= x"ff"; wait for clk_period;
566
                mac_rx_tdata <= x"ff"; wait for clk_period;
567
                -- DST IP
568
                mac_rx_tdata <= x"c0"; wait for clk_period;
569
                mac_rx_tdata <= x"a8"; wait for clk_period;
570
                mac_rx_tdata <= x"05"; wait for clk_period;
571
                mac_rx_tdata <= x"09"; wait for clk_period;
572
                -- SRC port
573
                mac_rx_tdata <= x"f4"; wait for clk_period;
574
                mac_rx_tdata <= x"9a"; wait for clk_period;
575
                -- DST port
576
                mac_rx_tdata <= x"26"; wait for clk_period;
577
                mac_rx_tdata <= x"94"; wait for clk_period;
578
                -- length
579
                mac_rx_tdata <= x"00"; wait for clk_period;
580
                mac_rx_tdata <= x"0d"; wait for clk_period;
581
                -- cks
582
                mac_rx_tdata <= x"8b"; wait for clk_period;
583
                mac_rx_tdata <= x"79"; wait for clk_period;
584
                -- user data
585
                mac_rx_tdata <= x"68"; wait for clk_period;
586
 
587
                -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
588
                assert udp_rx_int.hdr.is_valid = '1'                            report "T4: udp_rx_int.hdr.is_valid not set";
589
                assert udp_rx_int.hdr.data_length = x"0005"             report "T4: udp_rx_int.hdr.data_length not set correctly";
590
                assert udp_rx_int.hdr.src_ip_addr = x"ffffffff" report "T4: udp_rx_int.hdr.src_ip_addr not set correctly";
591
                assert udp_rx_int.hdr.src_port = x"f49a"                        report "T4: udp_rx_int.hdr.src_port not set correctly";
592
                assert udp_rx_int.hdr.dst_port = x"2694"                        report "T4: udp_rx_int.hdr.dst_port not set correctly";
593
 
594
                assert udp_rx_start_int = '1'                                                   report "T4: udp_rx_start not set";
595
                assert udp_rx_int.data.data_in_valid = '1'              report "T4: udp_rx_int.data.data_in_valid not set";
596
 
597
                assert ip_rx_hdr.is_valid = '1'                                 report "T4: ip_rx_hdr.is_valid not set";
598
                assert ip_rx_hdr.protocol = x"11"                               report "T4: ip_rx_hdr.protocol not set correctly";
599
                assert ip_rx_hdr.src_ip_addr = x"ffffffff"      report "T4: ip_rx.hdr.src_ip_addr not set correctly";
600
                assert ip_rx_hdr.num_frame_errors = x"00"       report "T4: ip_rx.hdr.num_frame_errors not set correctly";
601
                assert ip_rx_hdr.last_error_code = x"0"          report "T4: ip_rx.hdr.last_error_code not set correctly";
602
 
603
                -- put the rest of the user data
604
                mac_rx_tdata <= x"65"; wait for clk_period;
605
                mac_rx_tdata <= x"6c"; wait for clk_period;
606
                mac_rx_tdata <= x"6c"; wait for clk_period;
607
                mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
608
 
609
                assert udp_rx_int.data.data_in_last = '1'                       report "T4: udp_rx_int.data.data_in_last not set";
610
 
611
                mac_rx_tdata <= x"00";
612
                mac_rx_tlast <= '0';
613
                mac_rx_tvalid <= '0';
614
                wait for clk_period;
615
 
616
                report "T4: waiting for mac data tx";
617
                wait until mac_tx_tvalid = '1';
618
                report "T4: starting mac data tx";
619
                wait for clk_period;
620
 
621
                -- check the mac data being transmitted
622
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst mac 0";       wait for clk_period;
623
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst mac 1";       wait for clk_period;
624
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst mac 2";       wait for clk_period;
625
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst mac 3";       wait for clk_period;
626
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst mac 4";       wait for clk_period;
627
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst mac 5";       wait for clk_period;
628
 
629
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect src mac 0";       wait for clk_period;
630
                assert mac_tx_tdata = x"23"                                                     report "T4: incorrect src mac 1";       wait for clk_period;
631
                assert mac_tx_tdata = x"20"                                                     report "T4: incorrect src mac 2";       wait for clk_period;
632
                assert mac_tx_tdata = x"21"                                                     report "T4: incorrect src mac 3";       wait for clk_period;
633
                assert mac_tx_tdata = x"22"                                                     report "T4: incorrect src mac 4";       wait for clk_period;
634
                assert mac_tx_tdata = x"23"                                                     report "T4: incorrect src mac 5";       wait for clk_period;
635
 
636
                assert mac_tx_tdata = x"08"                                                     report "T4: incorrect pkt_type 0";      wait for clk_period;
637
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect pkt type 1";      wait for clk_period;
638
 
639
                assert mac_tx_tdata = x"45"                                                     report "T4: incorrect ver.hlen";                wait for clk_period;
640
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect srv type";                wait for clk_period;
641
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect len 0";                   wait for clk_period;
642
                assert mac_tx_tdata = x"20"                                                     report "T4: incorrect len 1";                   wait for clk_period;
643
 
644
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect ident 0";         wait for clk_period;
645
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect ident 1";         wait for clk_period;
646
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect flag&frag 0";     wait for clk_period;
647
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect flag&frag 1";     wait for clk_period;
648
 
649
                assert mac_tx_tdata = x"80"                                                     report "T4: incorrect TTL";                     wait for clk_period;
650
                assert mac_tx_tdata = x"11"                                                     report "T4: incorrect protocol";                wait for clk_period;
651
                assert mac_tx_tdata = x"75"                                                     report "T4: incorrect hdr.cks 0";       wait for clk_period;
652
                assert mac_tx_tdata = x"1c"                                                     report "T4: incorrect hdr.cks 1";       wait for clk_period;
653
 
654
                assert mac_tx_tdata = x"c0"                                                     report "T4: incorrect src ip 0";                wait for clk_period;
655
                assert mac_tx_tdata = x"a8"                                                     report "T4: incorrect src ip 1";                wait for clk_period;
656
                assert mac_tx_tdata = x"05"                                                     report "T4: incorrect src ip 2";                wait for clk_period;
657
                assert mac_tx_tdata = x"09"                                                     report "T4: incorrect src ip 3";                wait for clk_period;
658
 
659
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst ip 0";                wait for clk_period;
660
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst ip 1";                wait for clk_period;
661
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst ip 2";                wait for clk_period;
662
                assert mac_tx_tdata = x"ff"                                                     report "T4: incorrect dst ip 3";                wait for clk_period;
663
 
664
                assert mac_tx_tdata = x"26"                                                     report "T4: incorrect src port 0";      wait for clk_period;
665
                assert mac_tx_tdata = x"94"                                                     report "T4: incorrect src port 1";      wait for clk_period;
666
                assert mac_tx_tdata = x"f4"                                                     report "T4: incorrect dst port 0";      wait for clk_period;
667
                assert mac_tx_tdata = x"9a"                                                     report "T4: incorrect dst port 1";      wait for clk_period;
668
 
669
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect udp len 0";       wait for clk_period;
670
                assert mac_tx_tdata = x"0c"                                                     report "T4: incorrect udp len 1";       wait for clk_period;
671
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect udp cks 0";       wait for clk_period;
672
                assert mac_tx_tdata = x"00"                                                     report "T4: incorrect udp cks 1";       wait for clk_period;
673
 
674
                assert mac_tx_tdata = x"40"                                                     report "T4: incorrect udp data 0";      wait for clk_period;
675
                assert mac_tx_tdata = x"41"                                                     report "T4: incorrect udp data 1";      wait for clk_period;
676
 
677
                assert mac_tx_tdata = x"42"                                                     report "T4: incorrect udp data 2";
678
                assert mac_tx_tlast = '0'                                                                report "T4: tlast asserted too soon";   wait for clk_period;
679
                assert mac_tx_tdata = x"43"                                                     report "T4: incorrect udp data 3";
680
                assert mac_tx_tlast = '1'                                                               report "T4: tlast not asserted";                        wait for clk_period;
681
 
682
                assert udp_tx_result = IPTX_RESULT_SENT                 report "T4: TX did not complete";
683
 
684
                assert udp_rx_int.data.data_in_valid = '0'               report "T4: udp_rx_int.data.data_in_valid not cleared";
685
                assert udp_rx_int.data.data_in_last = '0'                        report "T4: udp_rx_int.data.data_in_last not cleared";
686
                assert udp_rx_start_int = '0'                                                    report "T4: udp_rx_start not cleared";
687
                assert ip_rx_hdr.num_frame_errors = x"00"                       report "T4: ip_rx_hdr.num_frame_errors non zero at end of test";
688
                assert ip_rx_hdr.last_error_code = x"0"                  report "T4: ip_rx_hdr.last_error_code indicates error at end of test";
689
                assert ip_pkt_count = x"03"                                                     report "T4: ip pkt cnt incorrect";
690
 
691
                ------------
692
                -- TEST 5 -- send UDP pkt with dst=bc addr to ensure we can receive broadcast tx
693
                ------------
694
 
695
                report "T5: Send UDP IP pkt dst ip_address bc, from port f49a to port 2694";
696
 
697
                mac_rx_tvalid <= '1';
698
                -- dst MAC (bc)
699
                mac_rx_tdata <= x"ff"; wait for clk_period;
700
                mac_rx_tdata <= x"ff"; wait for clk_period;
701
                mac_rx_tdata <= x"ff"; wait for clk_period;
702
                mac_rx_tdata <= x"ff"; wait for clk_period;
703
                mac_rx_tdata <= x"ff"; wait for clk_period;
704
                mac_rx_tdata <= x"ff"; wait for clk_period;
705
                -- src MAC
706
                mac_rx_tdata <= x"00"; wait for clk_period;
707
                mac_rx_tdata <= x"23"; wait for clk_period;
708
                mac_rx_tdata <= x"18"; wait for clk_period;
709
                mac_rx_tdata <= x"29"; wait for clk_period;
710
                mac_rx_tdata <= x"26"; wait for clk_period;
711
                mac_rx_tdata <= x"7c"; wait for clk_period;
712
                -- type
713
                mac_rx_tdata <= x"08"; wait for clk_period;             -- IP pkt
714
                mac_rx_tdata <= x"00"; wait for clk_period;
715
                -- ver & HL / service type
716
                mac_rx_tdata <= x"45"; wait for clk_period;
717
                mac_rx_tdata <= x"00"; wait for clk_period;
718
                -- total len
719
                mac_rx_tdata <= x"00"; wait for clk_period;
720
                mac_rx_tdata <= x"21"; wait for clk_period;
721
                -- ID
722
                mac_rx_tdata <= x"00"; wait for clk_period;
723
                mac_rx_tdata <= x"7a"; wait for clk_period;
724
                -- flags & frag
725
                mac_rx_tdata <= x"00"; wait for clk_period;
726
                mac_rx_tdata <= x"00"; wait for clk_period;
727
                -- TTL
728
                mac_rx_tdata <= x"80"; wait for clk_period;
729
                -- Protocol
730
                mac_rx_tdata <= x"11"; wait for clk_period;
731
                -- Header CKS
732
                mac_rx_tdata <= x"00"; wait for clk_period;
733
                mac_rx_tdata <= x"00"; wait for clk_period;
734
                -- SRC IP
735
                mac_rx_tdata <= x"c0"; wait for clk_period;
736
                mac_rx_tdata <= x"a8"; wait for clk_period;
737
                mac_rx_tdata <= x"05"; wait for clk_period;
738
                mac_rx_tdata <= x"01"; wait for clk_period;
739
                -- DST IP
740
                mac_rx_tdata <= x"ff"; wait for clk_period;
741
                mac_rx_tdata <= x"ff"; wait for clk_period;
742
                mac_rx_tdata <= x"ff"; wait for clk_period;
743
                mac_rx_tdata <= x"ff"; wait for clk_period;
744
                -- SRC port
745
                mac_rx_tdata <= x"f4"; wait for clk_period;
746
                mac_rx_tdata <= x"9a"; wait for clk_period;
747
                -- DST port
748
                mac_rx_tdata <= x"26"; wait for clk_period;
749
                mac_rx_tdata <= x"94"; wait for clk_period;
750
                -- length
751
                mac_rx_tdata <= x"00"; wait for clk_period;
752
                mac_rx_tdata <= x"0d"; wait for clk_period;
753
                -- cks
754
                mac_rx_tdata <= x"8b"; wait for clk_period;
755
                mac_rx_tdata <= x"79"; wait for clk_period;
756
                -- user data
757
                mac_rx_tdata <= x"68"; wait for clk_period;
758
 
759
                -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
760
                assert udp_rx_int.hdr.is_valid = '1'                            report "T5: udp_rx_int.hdr.is_valid not set";
761
                assert udp_rx_int.hdr.data_length = x"0005"             report "T5: udp_rx_int.hdr.data_length not set correctly";
762
                assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T5: udp_rx_int.hdr.src_ip_addr not set correctly";
763
                assert udp_rx_int.hdr.src_port = x"f49a"                        report "T5: udp_rx_int.hdr.src_port not set correctly";
764
                assert udp_rx_int.hdr.dst_port = x"2694"                        report "T5: udp_rx_int.hdr.dst_port not set correctly";
765
 
766
                assert udp_rx_start_int = '1'                                                   report "T5: udp_rx_start not set";
767
                assert udp_rx_int.data.data_in_valid = '1'              report "T5: udp_rx_int.data.data_in_valid not set";
768
 
769
                assert ip_rx_hdr.is_valid = '1'                                         report "T5: ip_rx_hdr.is_valid not set";
770
                assert ip_rx_hdr.protocol = x"11"                                       report "T5: ip_rx_hdr.protocol not set correctly";
771
                assert ip_rx_hdr.src_ip_addr = x"c0a80501"              report "T5: ip_rx.hdr.src_ip_addr not set correctly";
772
                assert ip_rx_hdr.num_frame_errors = x"00"               report "T5: ip_rx.hdr.num_frame_errors not set correctly";
773
                assert ip_rx_hdr.last_error_code = x"0"                  report "T5: ip_rx.hdr.last_error_code not set correctly";
774
 
775
                -- put the rest of the user data
776
                mac_rx_tdata <= x"65"; wait for clk_period;
777
                mac_rx_tdata <= x"6c"; wait for clk_period;
778
                mac_rx_tdata <= x"6c"; wait for clk_period;
779
                mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
780
 
781
                assert udp_rx_int.data.data_in_last = '1'                       report "T5: udp_rx_int.data.data_in_last not set";
782
 
783
                mac_rx_tdata <= x"00";
784
                mac_rx_tlast <= '0';
785
                mac_rx_tvalid <= '0';
786
 
787
                report "T5: waiting for mac data tx";
788
                if mac_tx_tvalid = '0' then
789
                        wait until mac_tx_tvalid = '1';
790
                        wait for clk_period;
791
                end if;
792
                report "T5: starting mac data tx";
793
 
794
                -- check the mac data being transmitted
795
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect dst mac 0";       wait for clk_period;
796
                assert mac_tx_tdata = x"23"                                                     report "T5: incorrect dst mac 1";       wait for clk_period;
797
                assert mac_tx_tdata = x"18"                                                     report "T5: incorrect dst mac 2";       wait for clk_period;
798
                assert mac_tx_tdata = x"29"                                                     report "T5: incorrect dst mac 3";       wait for clk_period;
799
                assert mac_tx_tdata = x"26"                                                     report "T5: incorrect dst mac 4";       wait for clk_period;
800
                assert mac_tx_tdata = x"7c"                                                     report "T5: incorrect dst mac 5";       wait for clk_period;
801
 
802
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect src mac 0";       wait for clk_period;
803
                assert mac_tx_tdata = x"23"                                                     report "T5: incorrect src mac 1";       wait for clk_period;
804
                assert mac_tx_tdata = x"20"                                                     report "T5: incorrect src mac 2";       wait for clk_period;
805
                assert mac_tx_tdata = x"21"                                                     report "T5: incorrect src mac 3";       wait for clk_period;
806
                assert mac_tx_tdata = x"22"                                                     report "T5: incorrect src mac 4";       wait for clk_period;
807
                assert mac_tx_tdata = x"23"                                                     report "T5: incorrect src mac 5";       wait for clk_period;
808
 
809
                assert mac_tx_tdata = x"08"                                                     report "T5: incorrect pkt_type 0";      wait for clk_period;
810
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect pkt type 1";      wait for clk_period;
811
 
812
                assert mac_tx_tdata = x"45"                                                     report "T5: incorrect ver.hlen";                wait for clk_period;
813
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect srv type";                wait for clk_period;
814
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect len 0";                   wait for clk_period;
815
                assert mac_tx_tdata = x"20"                                                     report "T5: incorrect len 1";                   wait for clk_period;
816
 
817
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect ident 0";         wait for clk_period;
818
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect ident 1";         wait for clk_period;
819
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect flag&frag 0";     wait for clk_period;
820
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect flag&frag 1";     wait for clk_period;
821
 
822
                assert mac_tx_tdata = x"80"                                                     report "T5: incorrect TTL";                     wait for clk_period;
823
                assert mac_tx_tdata = x"11"                                                     report "T5: incorrect protocol";                wait for clk_period;
824
                assert mac_tx_tdata = x"af"                                                     report "T5: incorrect hdr.cks 0";       wait for clk_period;
825
                assert mac_tx_tdata = x"72"                                                     report "T5: incorrect hdr.cks 1";       wait for clk_period;
826
 
827
                assert mac_tx_tdata = x"c0"                                                     report "T5: incorrect src ip 0";                wait for clk_period;
828
                assert mac_tx_tdata = x"a8"                                                     report "T5: incorrect src ip 1";                wait for clk_period;
829
                assert mac_tx_tdata = x"05"                                                     report "T5: incorrect src ip 2";                wait for clk_period;
830
                assert mac_tx_tdata = x"09"                                                     report "T5: incorrect src ip 3";                wait for clk_period;
831
 
832
                assert mac_tx_tdata = x"c0"                                                     report "T5: incorrect dst ip 0";                wait for clk_period;
833
                assert mac_tx_tdata = x"a8"                                                     report "T5: incorrect dst ip 1";                wait for clk_period;
834
                assert mac_tx_tdata = x"05"                                                     report "T5: incorrect dst ip 2";                wait for clk_period;
835
                assert mac_tx_tdata = x"01"                                                     report "T5: incorrect dst ip 3";                wait for clk_period;
836
 
837
                assert mac_tx_tdata = x"26"                                                     report "T5: incorrect src port 0";      wait for clk_period;
838
                assert mac_tx_tdata = x"94"                                                     report "T5: incorrect src port 1";      wait for clk_period;
839
                assert mac_tx_tdata = x"f4"                                                     report "T5: incorrect dst port 0";      wait for clk_period;
840
                assert mac_tx_tdata = x"9a"                                                     report "T5: incorrect dst port 1";      wait for clk_period;
841
 
842
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect udp len 0";       wait for clk_period;
843
                assert mac_tx_tdata = x"0c"                                                     report "T5: incorrect udp len 1";       wait for clk_period;
844
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect udp cks 0";       wait for clk_period;
845
                assert mac_tx_tdata = x"00"                                                     report "T5: incorrect udp cks 1";       wait for clk_period;
846
 
847
                assert mac_tx_tdata = x"50"                                                     report "T5: incorrect udp data 0";      wait for clk_period;
848
                assert mac_tx_tdata = x"51"                                                     report "T5: incorrect udp data 1";      wait for clk_period;
849
 
850
                assert mac_tx_tdata = x"52"                                                     report "T5: incorrect udp data 2";
851
                assert mac_tx_tlast = '0'                                                                report "T5: tlast asserted too soon";   wait for clk_period;
852
                assert mac_tx_tdata = x"53"                                                     report "T5: incorrect udp data 3";
853
                assert mac_tx_tlast = '1'                                                               report "T5: tlast not asserted";                        wait for clk_period;
854
 
855
                assert udp_tx_result = IPTX_RESULT_SENT                 report "T5: TX did not complete";
856
 
857
                assert udp_rx_int.data.data_in_valid = '0'               report "T5: udp_rx_int.data.data_in_valid not cleared";
858
                assert udp_rx_int.data.data_in_last = '0'                        report "T5: udp_rx_int.data.data_in_last not cleared";
859
                assert udp_rx_start_int = '0'                                                    report "T5: udp_rx_start not cleared";
860
                assert ip_rx_hdr.num_frame_errors = x"00"                       report "T5: ip_rx_hdr.num_frame_errors non zero at end of test";
861
                assert ip_rx_hdr.last_error_code = x"0"                  report "T5: ip_rx_hdr.last_error_code indicates error at end of test";
862
                assert ip_pkt_count = x"04"                                                     report "T5: ip pkt cnt incorrect";
863
 
864 2 pjf
                report "--- end of tests ---";
865
      wait;
866
   end process;
867
 
868 6 pjf
        -- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
869 2 pjf
 
870
                -- TX response process - COMB
871
   tx_proc_combinatorial: process(
872
                -- inputs
873
                udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX,
874
                -- state
875
                state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
876
                -- controls
877
                next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
878
                set_tx_started, set_tx_fin
879
                )
880
   begin
881
                -- set output_followers
882
                udp_tx_int.hdr <= tx_hdr;
883
                udp_tx_int.data.data_out_last <= set_last;
884
                udp_tx_start_int <= tx_start_reg;
885
 
886
                -- set control signal defaults
887
                next_state <= IDLE;
888
                set_state <= '0';
889
                set_count <= HOLD;
890
                set_hdr <= '0';
891
                set_tx_start <= HOLD;
892
                set_last <= '0';
893
                set_tx_started <= HOLD;
894
                set_tx_fin <= HOLD;
895
 
896
                -- FSM
897
                case state is
898
 
899
                        when IDLE =>
900
                                udp_tx_int.data.data_out <= (others => '0');
901
                                udp_tx_int.data.data_out_valid <= '0';
902
                                if udp_rx_start_int = '1' or PBTX = '1' then
903
                                        set_tx_started <= SET;
904
                                        set_hdr <= '1';
905
                                        set_tx_start <= SET;
906
                                        set_tx_fin <= CLR;
907
                                        set_count <= RST;
908
                                        next_state <= DATA_OUT;
909
                                        set_state <= '1';
910
                                end if;
911
 
912
                        when DATA_OUT =>
913 6 pjf
                                if ip_rx_hdr.is_broadcast = '1' then
914
                                        udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";
915
                                else
916
                                        udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
917
                                end if;
918 2 pjf
                                udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
919
                                if udp_tx_data_out_ready_int = '1' then
920
                                        set_tx_start <= CLR;
921
                                        if unsigned(count) = x"03" then
922
                                                set_last <= '1';
923
                                                set_tx_fin <= SET;
924
                                                set_tx_started <= CLR;
925
                                                next_state <= IDLE;
926
                                                set_state <= '1';
927
                                        else
928
                                                set_count <= INCR;
929
                                        end if;
930
                                end if;
931
 
932
                end case;
933
        end process;
934
 
935
 
936
 
937
   -- TX response process - SEQ
938
   tx_proc_sequential: process(clk_int)
939
   begin
940
                if rising_edge(clk_int) then
941
                        if reset = '1' then
942
                                -- reset state variables
943
                                state <= IDLE;
944
                                count <= x"00";
945
                                tx_start_reg <= '0';
946
                                tx_hdr.dst_ip_addr <= (others => '0');
947
                                tx_hdr.dst_port <= (others => '0');
948
                                tx_hdr.src_port <= (others => '0');
949
                                tx_hdr.data_length <= (others => '0');
950
                                tx_hdr.checksum <= (others => '0');
951
                                tx_started_reg <= '0';
952
                                tx_fin_reg <= '0';
953
                                PBTX_LED <= '0';
954
                        else
955
                                PBTX_LED <= PBTX;
956
 
957
                                -- Next rx_state processing
958
                                if set_state = '1' then
959
                                        state <= next_state;
960
                                else
961
                                        state <= state;
962
                                end if;
963
 
964
                                -- count processing
965
                                case set_count is
966
                                        when RST =>             count <= x"00";
967
                                        when INCR =>            count <= count + 1;
968
                                        when HOLD =>            count <= count;
969
                                end case;
970
 
971
                                -- set tx hdr
972
                                if set_hdr = '1' then
973
                                        tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
974
                                        tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
975
                                        tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
976
                                        tx_hdr.data_length <= x"0004";
977
                                        tx_hdr.checksum <= x"0000";
978
                                else
979
                                        tx_hdr <= tx_hdr;
980
                                end if;
981
 
982
                                -- set tx start signal
983
                                case set_tx_start is
984
                                        when SET  => tx_start_reg <= '1';
985
                                        when CLR  => tx_start_reg <= '0';
986
                                        when HOLD => tx_start_reg <= tx_start_reg;
987
                                end case;
988
 
989
                                -- set tx started signal
990
                                case set_tx_started is
991
                                        when SET  => tx_started_reg <= '1';
992
                                        when CLR  => tx_started_reg <= '0';
993
                                        when HOLD => tx_started_reg <= tx_started_reg;
994
                                end case;
995
 
996
                                -- set tx finished signal
997
                                case set_tx_fin is
998
                                        when SET  => tx_fin_reg <= '1';
999
                                        when CLR  => tx_fin_reg <= '0';
1000
                                        when HOLD => tx_fin_reg <= tx_fin_reg;
1001
                                end case;
1002
 
1003
 
1004
                        end if;
1005
                end if;
1006
 
1007
        end process;
1008
 
1009
END;

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