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--------------------------------------------------------------------------------
-- Project    : low latency UDP
-- File       : xv6mac_straight
-- Version    : 0.0
-------------------------------------------------------------------------------
--
--
-- Description:  This is an adaptation of the Xilinx V6 MAC layer, but without the FIFOs
--
--
--
--    ---------------------------------------------------------------------
--    | EXAMPLE DESIGN WRAPPER                                            |
--    |           --------------------------------------------------------|
--    |           |FIFO BLOCK WRAPPER                                     |
--    |           |                                                       |
--    |           |                                                       |
--    |           |              -----------------------------------------|
--    |           |              | BLOCK LEVEL WRAPPER                    |
--    |           |              |    ---------------------               |
--    |           |              |    |   V6 EMAC CORE    |               |
--    |           |              |    |                   |               |
--    |           |              |    |                   |               |
--    |           |              |    |                   |               |
--    |           |              |    |                   |               |
--    |           |              |    |                   |               |
--    | |      |  |              |    |                   |  ---------    |
--    | |      |->|->----------->|--|--->| Tx            Tx  |--|       |--->|
--    | |      |  |              |    | AXI-S         PHY |  |       |    |
--    | |      |  |              |    | I/F           I/F |  |       |    |
--    | |      |  |              |    |                   |  | PHY   |    |
--    | |      |  |              |    |                   |  | I/F   |    |
--    | |      |  |              |    |                   |  |       |    |
--    | |      |  |              |    | Rx            Rx  |  |       |    |
--    | |      |  |              |    | AX)-S         PHY |  |       |    |
--    | |      |<-|<-------------|----| I/F           I/F |<-|       |<---|
--    | |      |  |              |    |                   |  ---------    |
--    | --------  |              |    ---------------------               |
--    |           |              |                                        |
--    |           |              -----------------------------------------|
--    |           --------------------------------------------------------|
--    ---------------------------------------------------------------------
--
--------------------------------------------------------------------------------
 
library unisim;
use unisim.vcomponents.all;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity xv6mac_straight is
    port (
                -- System controls
                ------------------
      glbl_rst                      : in  std_logic;                                    -- asynchronous reset
      mac_reset                         : in  std_logic;                                                        -- reset mac layer
      clk_in_p                                  : in  std_logic;                                        -- 200MHz clock input from board
      clk_in_n                                  : in  std_logic;
 
                -- MAC Transmitter (AXI-S) Interface
      ---------------------------------------------
      mac_tx_clock                              : out  std_logic;                                                       -- data sampled on rising edge
      mac_tx_tdata                              : in  std_logic_vector(7 downto 0);      -- data byte to tx
      mac_tx_tvalid                             : in  std_logic;                                                        -- tdata is valid
      mac_tx_tready                             : out std_logic;                                                        -- mac is ready to accept data
      mac_tx_tlast                              : in  std_logic;                                                        -- indicates last byte of frame
 
      -- MAC Receiver (AXI-S) Interface
      ------------------------------------------
      mac_rx_clock                              : out  std_logic;                                                       -- data valid on rising edge
      mac_rx_tdata                              : out std_logic_vector(7 downto 0);      -- data byte received
      mac_rx_tvalid                             : out std_logic;                                                        -- indicates tdata is valid
      mac_rx_tready                             : in  std_logic;                                                        -- tells mac that we are ready to take data
      mac_rx_tlast                              : out std_logic;                                                        -- indicates last byte of the trame
 
      -- GMII Interface
      -----------------     
      phy_resetn                                : out std_logic;
      gmii_txd                      : out std_logic_vector(7 downto 0);
      gmii_tx_en                    : out std_logic;
      gmii_tx_er                    : out std_logic;
      gmii_tx_clk                   : out std_logic;
      gmii_rxd                      : in  std_logic_vector(7 downto 0);
      gmii_rx_dv                    : in  std_logic;
      gmii_rx_er                    : in  std_logic;
      gmii_rx_clk                   : in  std_logic;
      gmii_col                      : in  std_logic;
      gmii_crs                      : in  std_logic;
      mii_tx_clk                    : in  std_logic
                );
end xv6mac_straight;
 
architecture wrapper of xv6mac_straight is
 
  ------------------------------------------------------------------------------
  -- Component declaration for the internal mac layer
  ------------------------------------------------------------------------------
  component v6_emac_v2_1_fifo_block    --ok
   port(
      gtx_clk                    : in  std_logic;
      -- Receiver Statistics Interface
      -----------------------------------------
      rx_mac_aclk                : out std_logic;
      rx_reset                   : out std_logic;
      rx_statistics_vector       : out std_logic_vector(27 downto 0);
      rx_statistics_valid        : out std_logic;
 
      -- Receiver (AXI-S) Interface
      ------------------------------------------
      rx_fifo_clock              : in  std_logic;
      rx_fifo_resetn             : in  std_logic;
      rx_axis_fifo_tdata         : out std_logic_vector(7 downto 0);
      rx_axis_fifo_tvalid        : out std_logic;
      rx_axis_fifo_tready        : in  std_logic;
      rx_axis_fifo_tlast         : out std_logic;
 
      -- Transmitter Statistics Interface
      --------------------------------------------
      tx_mac_aclk                : out std_logic;
      tx_reset                   : out std_logic;
      tx_ifg_delay               : in  std_logic_vector(7 downto 0);
      tx_statistics_vector       : out std_logic_vector(31 downto 0);
      tx_statistics_valid        : out std_logic;
 
      -- Transmitter (AXI-S) Interface
      ---------------------------------------------
      tx_fifo_clock              : in  std_logic;
      tx_fifo_resetn             : in  std_logic;
      tx_axis_fifo_tdata         : in  std_logic_vector(7 downto 0);
      tx_axis_fifo_tvalid        : in  std_logic;
      tx_axis_fifo_tready        : out std_logic;
      tx_axis_fifo_tlast         : in  std_logic;
 
      -- MAC Control Interface
      --------------------------
      pause_req                  : in  std_logic;
      pause_val                  : in  std_logic_vector(15 downto 0);
 
      -- Reference clock for IDELAYCTRL's
      refclk                     : in  std_logic;
 
      -- GMII Interface
      -------------------
      gmii_txd                  : out std_logic_vector(7 downto 0);
      gmii_tx_en                : out std_logic;
      gmii_tx_er                : out std_logic;
      gmii_tx_clk               : out std_logic;
      gmii_rxd                  : in  std_logic_vector(7 downto 0);
      gmii_rx_dv                : in  std_logic;
      gmii_rx_er                : in  std_logic;
      gmii_rx_clk               : in  std_logic;
      gmii_col                  : in  std_logic;
      gmii_crs                  : in  std_logic;
      mii_tx_clk                : in  std_logic;
 
      -- Initial Unicast Address Value
      unicast_address           : in  std_logic_vector(47 downto 0);
 
 
      -- asynchronous reset
      glbl_rstn                  : in  std_logic;
      rx_axi_rstn                : in  std_logic;
      tx_axi_rstn                : in  std_logic
 
      );
  end component;
 
 
 
 
 
  ------------------------------------------------------------------------------
  -- Component Declaration for the Clock generator
  ------------------------------------------------------------------------------
 
   component clk_wiz_v2_1 --ok
   port (
      -- Clock in port
      CLK_IN1_P                 : in  std_logic;
      CLK_IN1_N                 : in  std_logic;
      -- Clock out ports
      CLK_OUT1                  : out std_logic;
      CLK_OUT2                  : out std_logic;
      CLK_OUT3                  : out std_logic;
      -- Status and control signals
      RESET                     : in  std_logic;
      LOCKED                    : out std_logic
   );
   end component;
 
 
 
 
 
   -----------------------------------------------------------------------------
   -- Component Declaration for the GMII IOB logic
   -----------------------------------------------------------------------------
 
 
  ------------------------------------------------------------------------------
  -- Component declaration for the synchroniser
  ------------------------------------------------------------------------------
  component sync_block --ok
  port (
     clk                        : in  std_logic;
     data_in                    : in  std_logic;
     data_out                   : out std_logic
  );
  end component;
 
 
 
  ------------------------------------------------------------------------------
  -- Component declaration for the reset synchroniser
  ------------------------------------------------------------------------------
  component reset_sync --ok
  port (
     reset_in                   : in  std_logic;    -- Active high asynchronous reset
     enable                     : in  std_logic;
     clk                        : in  std_logic;    -- clock to be sync'ed to
     reset_out                  : out std_logic     -- "Synchronised" reset signal
  );
  end component;
 
 
   ------------------------------------------------------------------------------
   -- Constants used in this top level wrapper.
   ------------------------------------------------------------------------------
   constant BOARD_PHY_ADDR                  : std_logic_vector(7 downto 0)  := "00000111";
 
 
   ------------------------------------------------------------------------------
   -- internal signals used in this top level wrapper.
   ------------------------------------------------------------------------------
 
   -- example design clocks
   signal gtx_clk_bufg                      : std_logic;
   signal refclk_bufg                       : std_logic;
   signal rx_mac_aclk                       : std_logic;
 
        -- tx handshaking
        signal mac_tx_tready_int                                                : std_logic;
        signal tx_full_reg                                                              : std_logic;
        signal tx_full_val                                                              : std_logic;
        signal tx_data_reg                                                              : std_logic_vector(7 downto 0);
        signal tx_last_reg                                                              : std_logic;
        signal set_tx_reg                                                                       : std_logic;
 
 
   signal phy_resetn_int                    : std_logic;
 
   -- resets (and reset generation)
   signal local_chk_reset                   : std_logic;
   signal chk_reset_int                     : std_logic;
   signal chk_pre_resetn                    : std_logic := '0';
   signal chk_resetn                        : std_logic := '0';
   signal dcm_locked                        : std_logic;
        signal tx_fifo_resetn                                                   : std_logic;
        signal rx_fifo_resetn                                                   : std_logic;
 
   signal glbl_rst_int                      : std_logic;
   signal phy_reset_count                   : unsigned(5 downto 0);
   signal glbl_rst_intn                     : std_logic;
 
        -- pipeline register for RX signals
        signal rx_data_val                                                              : std_logic_vector(7 downto 0);
        signal rx_tvalid_val                                                            : std_logic;
        signal rx_tlast_val                                                             : std_logic;
        signal rx_data_reg                                                              : std_logic_vector(7 downto 0);
        signal rx_tvalid_reg                                                            : std_logic;
        signal rx_tlast_reg                                                             : std_logic;
        signal rx_fifo_clock                                                            : std_logic;
 
  attribute keep : string;
  attribute keep of gtx_clk_bufg             : signal is "true";
  attribute keep of refclk_bufg              : signal is "true";
  attribute keep of mac_tx_tready_int        : signal is "true";
  attribute keep of tx_full_reg                 : signal is "true";
 
 
  ------------------------------------------------------------------------------
  -- Begin architecture
  ------------------------------------------------------------------------------
 
begin
 
        combinatorial: process (
                rx_data_reg, rx_tvalid_reg, rx_tlast_reg,
                mac_tx_tvalid, mac_tx_tready_int, tx_full_reg, tx_full_val, set_tx_reg
                )
        begin
                -- output followers
      mac_rx_tdata  <= rx_data_reg;
      mac_rx_tvalid <= rx_tvalid_reg;
      mac_rx_tlast  <= rx_tlast_reg;
                mac_tx_tready <= not (tx_full_reg and not mac_tx_tready_int);           -- if not full, we are ready to accept
 
                -- control defaults
                tx_full_val <= tx_full_reg;
                set_tx_reg <= '0';
 
                -- tx handshaking logic
                if mac_tx_tvalid = '1' then
                        tx_full_val <= '1';
                        set_tx_reg <= '1';
                elsif mac_tx_tready_int = '1' then
                        tx_full_val <= '0';
                end if;
 
        end process;
 
   sequential: process(gtx_clk_bufg)
   begin
                if rising_edge(gtx_clk_bufg) then
                        if chk_resetn = '0' then
                                -- reset state variables
                                rx_data_reg <= (others => '0');
                                rx_tvalid_reg <= '0';
                                rx_tlast_reg <= '0';
                                tx_full_reg <= '0';
                                tx_data_reg <= (others => '0');
                                tx_last_reg <= '0';
                        else
                                -- register rx data
                                rx_data_reg <= rx_data_val;
                                rx_tvalid_reg <= rx_tvalid_val;
                                rx_tlast_reg <= rx_tlast_val;
 
                                -- process tx tvalid and tready
                                tx_full_reg <= tx_full_val;
                                if set_tx_reg = '1' then
                                        tx_data_reg <= mac_tx_tdata;
                                        tx_last_reg <= mac_tx_tlast;
                                else
                                        tx_data_reg <= tx_data_reg;
                                        tx_last_reg <= tx_last_reg;
                                end if;
                        end if;
                end if;
        end process;
 
   ------------------------------------------------------------------------------
   -- Instantiate the Tri-Mode EMAC Block wrapper
   ------------------------------------------------------------------------------
   v6emac_fifo_block : v6_emac_v2_1_fifo_block   --ok
   port map(
 
      gtx_clk               => gtx_clk_bufg,
      -- Receiver Statistics Interface
      -----------------------------------------
      rx_mac_aclk           => open,
      rx_reset              => open,
      rx_statistics_vector  => open,
      rx_statistics_valid   => open,
 
      -- Receiver (AXI-S) Interface
      ------------------------------------------
      rx_fifo_clock             => gtx_clk_bufg,
      rx_fifo_resetn            => chk_resetn,
      rx_axis_fifo_tdata        => rx_data_val,
      rx_axis_fifo_tvalid       => rx_tvalid_val,
      rx_axis_fifo_tready       => mac_rx_tready,
      rx_axis_fifo_tlast        => rx_tlast_val,
 
      -- Transmitter Statistics Interface
      --------------------------------------------
      tx_mac_aclk               => open,
      tx_reset                  => open,
      tx_ifg_delay              => x"12",
      tx_statistics_vector      => open,
      tx_statistics_valid       => open,
 
      -- Transmitter (AXI-S) Interface
      ---------------------------------------------
      tx_fifo_clock              => gtx_clk_bufg,
      tx_fifo_resetn             => chk_resetn,
      tx_axis_fifo_tdata         => tx_data_reg,
      tx_axis_fifo_tvalid        => tx_full_reg,
      tx_axis_fifo_tready        => mac_tx_tready_int,
      tx_axis_fifo_tlast         => tx_last_reg,
 
      -- MAC Control Interface
      --------------------------
      pause_req             => '0',
      pause_val             => x"0000",
 
      -- Reference clock for IDELAYCTRL's
      refclk        => refclk_bufg,
 
      -- GMII Interface
      gmii_txd              => gmii_txd,
      gmii_tx_en            => gmii_tx_en,
      gmii_tx_er            => gmii_tx_er,
      gmii_tx_clk           => gmii_tx_clk,
      gmii_rxd              => gmii_rxd,
      gmii_rx_dv            => gmii_rx_dv,
      gmii_rx_er            => gmii_rx_er,
      gmii_rx_clk           => gmii_rx_clk,
      gmii_col              => gmii_col,
      gmii_crs              => gmii_crs,
      mii_tx_clk            => mii_tx_clk,
 
      -- Initial Unicast Address Value
      unicast_address       => x"FFFFFFFFFFFF",
 
 
      -- asynchronous reset
      glbl_rstn             => chk_resetn,
      rx_axi_rstn           => '1',
      tx_axi_rstn           => '1'
 
   );
 
 
   ------------------------------------------------------------------------------
   -- Clock logic to generate required clocks from the 200MHz on board
   -- if 125MHz is available directly this can be removed
   ------------------------------------------------------------------------------
   clock_generator : clk_wiz_v2_1
   port map (
      -- Clock in ports
      CLK_IN1_P         => clk_in_p,
      CLK_IN1_N         => clk_in_n,
      -- Clock out ports
      CLK_OUT1          => gtx_clk_bufg,
      CLK_OUT2          => open,
      CLK_OUT3          => refclk_bufg,
      -- Status and control signals
      RESET             => glbl_rst,
      LOCKED            => dcm_locked
   );
 
   -----------------
   -- global reset
   glbl_reset_gen : reset_sync
   port map (
      reset_in          => glbl_rst,
      enable            => dcm_locked,
      clk               => gtx_clk_bufg,
      reset_out         => glbl_rst_int
   );
 
   glbl_rst_intn <= not glbl_rst_int;
 
   -- generate the user side clocks
        mac_tx_clock <= gtx_clk_bufg;
        mac_rx_clock <= gtx_clk_bufg;
 
   ------------------------------------------------------------------------------
   -- Generate resets 
   ------------------------------------------------------------------------------
   -- in each case the async reset is first captured and then synchronised
 
 
  local_chk_reset <= glbl_rst or mac_reset;
 
  -----------------
  -- data check reset
   chk_reset_gen : reset_sync
   port map (
       reset_in         => local_chk_reset,
       enable           => dcm_locked,
       clk              => gtx_clk_bufg,
       reset_out        => chk_reset_int
   );
 
   -- Create fully synchronous reset in the gtx clock domain.
   gen_chk_reset : process (gtx_clk_bufg)
   begin
     if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
       if chk_reset_int = '1' then
         chk_pre_resetn   <= '0';
         chk_resetn       <= '0';
       else
         chk_pre_resetn   <= '1';
         chk_resetn       <= chk_pre_resetn;
       end if;
     end if;
   end process gen_chk_reset;
 
 
 
   -----------------
   -- PHY reset
   -- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
   -- this is derived using the 125MHz available and a 6 bit counter
   gen_phy_reset : process (gtx_clk_bufg)
   begin
     if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
       if glbl_rst_intn = '0' then
         phy_resetn_int       <= '0';
         phy_reset_count      <= (others => '0');
       else
          if phy_reset_count /= "111111" then
             phy_reset_count <= phy_reset_count + "000001";
          else
             phy_resetn_int   <= '1';
          end if;
       end if;
     end if;
   end process gen_phy_reset;
 
   phy_resetn <= phy_resetn_int;
 
 
end wrapper;

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Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [contrib/] [Headers sometimes have errors/] [xv6mac_straight.vhd] - Blame information for rev 35

Line No.	Rev	Author	Line
1	35	pjf	`--------------------------------------------------------------------------------`
2			`-- Project : low latency UDP`
3			`-- File : xv6mac_straight`
4			`-- Version : 0.0`
5			`-------------------------------------------------------------------------------`
6			`--`
7			`--`
8			`-- Description: This is an adaptation of the Xilinx V6 MAC layer, but without the FIFOs`
9			`--`
10			`--`
11			`--`
12			`-- ---------------------------------------------------------------------`
13			`-- \| EXAMPLE DESIGN WRAPPER \|`
14			`-- \| --------------------------------------------------------\|`
15			`-- \| \|FIFO BLOCK WRAPPER \|`
16			`-- \| \| \|`
17			`-- \| \| \|`
18			`-- \| \| -----------------------------------------\|`
19			`-- \| \| \| BLOCK LEVEL WRAPPER \|`
20			`-- \| \| \| --------------------- \|`
21			`-- \| \| \| \| V6 EMAC CORE \| \|`
22			`-- \| \| \| \| \| \|`
23			`-- \| \| \| \| \| \|`
24			`-- \| \| \| \| \| \|`
25			`-- \| \| \| \| \| \|`
26			`-- \| \| \| \| \| \|`
27			`-- \| \| \| \| \| \| \| --------- \|`
28			`-- \| \| \|->\|->----------->\|--\|--->\| Tx Tx \|--\| \|--->\|`
29			`-- \| \| \| \| \| \| AXI-S PHY \| \| \| \|`
30			`-- \| \| \| \| \| \| I/F I/F \| \| \| \|`
31			`-- \| \| \| \| \| \| \| \| PHY \| \|`
32			`-- \| \| \| \| \| \| \| \| I/F \| \|`
33			`-- \| \| \| \| \| \| \| \| \| \|`
34			`-- \| \| \| \| \| \| Rx Rx \| \| \| \|`
35			`-- \| \| \| \| \| \| AX)-S PHY \| \| \| \|`
36			`-- \| \| \|<-\|<-------------\|----\| I/F I/F \|<-\| \|<---\|`
37			`-- \| \| \| \| \| \| \| --------- \|`
38			`-- \| -------- \| \| --------------------- \|`
39			`-- \| \| \| \|`
40			`-- \| \| -----------------------------------------\|`
41			`-- \| --------------------------------------------------------\|`
42			`-- ---------------------------------------------------------------------`
43			`--`
44			`--------------------------------------------------------------------------------`
45
46			`library unisim;`
47			`use unisim.vcomponents.all;`
48
49			`library ieee;`
50			`use ieee.std_logic_1164.all;`
51			`use ieee.std_logic_unsigned.all;`
52			`use ieee.numeric_std.all;`
53
54			`entity xv6mac_straight is`
55			`port (`
56			`-- System controls`
57			`------------------`
58			`glbl_rst : in std_logic; -- asynchronous reset`
59			`mac_reset : in std_logic; -- reset mac layer`
60			`clk_in_p : in std_logic; -- 200MHz clock input from board`
61			`clk_in_n : in std_logic;`
62
63			`-- MAC Transmitter (AXI-S) Interface`
64			`---------------------------------------------`
65			`mac_tx_clock : out std_logic; -- data sampled on rising edge`
66			`mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx`
67			`mac_tx_tvalid : in std_logic; -- tdata is valid`
68			`mac_tx_tready : out std_logic; -- mac is ready to accept data`
69			`mac_tx_tlast : in std_logic; -- indicates last byte of frame`
70
71			`-- MAC Receiver (AXI-S) Interface`
72			`------------------------------------------`
73			`mac_rx_clock : out std_logic; -- data valid on rising edge`
74			`mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received`
75			`mac_rx_tvalid : out std_logic; -- indicates tdata is valid`
76			`mac_rx_tready : in std_logic; -- tells mac that we are ready to take data`
77			`mac_rx_tlast : out std_logic; -- indicates last byte of the trame`
78
79			`-- GMII Interface`
80			`-----------------`
81			`phy_resetn : out std_logic;`
82			`gmii_txd : out std_logic_vector(7 downto 0);`
83			`gmii_tx_en : out std_logic;`
84			`gmii_tx_er : out std_logic;`
85			`gmii_tx_clk : out std_logic;`
86			`gmii_rxd : in std_logic_vector(7 downto 0);`
87			`gmii_rx_dv : in std_logic;`
88			`gmii_rx_er : in std_logic;`
89			`gmii_rx_clk : in std_logic;`
90			`gmii_col : in std_logic;`
91			`gmii_crs : in std_logic;`
92			`mii_tx_clk : in std_logic`
93			`);`
94			`end xv6mac_straight;`
95
96			`architecture wrapper of xv6mac_straight is`
97
98			`------------------------------------------------------------------------------`
99			`-- Component declaration for the internal mac layer`
100			`------------------------------------------------------------------------------`
101			`component v6_emac_v2_1_fifo_block --ok`
102			`port(`
103			`gtx_clk : in std_logic;`
104			`-- Receiver Statistics Interface`
105			`-----------------------------------------`
106			`rx_mac_aclk : out std_logic;`
107			`rx_reset : out std_logic;`
108			`rx_statistics_vector : out std_logic_vector(27 downto 0);`
109			`rx_statistics_valid : out std_logic;`
110
111			`-- Receiver (AXI-S) Interface`
112			`------------------------------------------`
113			`rx_fifo_clock : in std_logic;`
114			`rx_fifo_resetn : in std_logic;`
115			`rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);`
116			`rx_axis_fifo_tvalid : out std_logic;`
117			`rx_axis_fifo_tready : in std_logic;`
118			`rx_axis_fifo_tlast : out std_logic;`
119
120			`-- Transmitter Statistics Interface`
121			`--------------------------------------------`
122			`tx_mac_aclk : out std_logic;`
123			`tx_reset : out std_logic;`
124			`tx_ifg_delay : in std_logic_vector(7 downto 0);`
125			`tx_statistics_vector : out std_logic_vector(31 downto 0);`
126			`tx_statistics_valid : out std_logic;`
127
128			`-- Transmitter (AXI-S) Interface`
129			`---------------------------------------------`
130			`tx_fifo_clock : in std_logic;`
131			`tx_fifo_resetn : in std_logic;`
132			`tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);`
133			`tx_axis_fifo_tvalid : in std_logic;`
134			`tx_axis_fifo_tready : out std_logic;`
135			`tx_axis_fifo_tlast : in std_logic;`
136
137			`-- MAC Control Interface`
138			`--------------------------`
139			`pause_req : in std_logic;`
140			`pause_val : in std_logic_vector(15 downto 0);`
141
142			`-- Reference clock for IDELAYCTRL's`
143			`refclk : in std_logic;`
144
145			`-- GMII Interface`
146			`-------------------`
147			`gmii_txd : out std_logic_vector(7 downto 0);`
148			`gmii_tx_en : out std_logic;`
149			`gmii_tx_er : out std_logic;`
150			`gmii_tx_clk : out std_logic;`
151			`gmii_rxd : in std_logic_vector(7 downto 0);`
152			`gmii_rx_dv : in std_logic;`
153			`gmii_rx_er : in std_logic;`
154			`gmii_rx_clk : in std_logic;`
155			`gmii_col : in std_logic;`
156			`gmii_crs : in std_logic;`
157			`mii_tx_clk : in std_logic;`
158
159			`-- Initial Unicast Address Value`
160			`unicast_address : in std_logic_vector(47 downto 0);`
161
162
163			`-- asynchronous reset`
164			`glbl_rstn : in std_logic;`
165			`rx_axi_rstn : in std_logic;`
166			`tx_axi_rstn : in std_logic`
167
168			`);`
169			`end component;`
170
171
172
173
174
175			`------------------------------------------------------------------------------`
176			`-- Component Declaration for the Clock generator`
177			`------------------------------------------------------------------------------`
178
179			`component clk_wiz_v2_1 --ok`
180			`port (`
181			`-- Clock in port`
182			`CLK_IN1_P : in std_logic;`
183			`CLK_IN1_N : in std_logic;`
184			`-- Clock out ports`
185			`CLK_OUT1 : out std_logic;`
186			`CLK_OUT2 : out std_logic;`
187			`CLK_OUT3 : out std_logic;`
188			`-- Status and control signals`
189			`RESET : in std_logic;`
190			`LOCKED : out std_logic`
191			`);`
192			`end component;`
193
194
195
196
197
198			`-----------------------------------------------------------------------------`
199			`-- Component Declaration for the GMII IOB logic`
200			`-----------------------------------------------------------------------------`
201
202
203			`------------------------------------------------------------------------------`
204			`-- Component declaration for the synchroniser`
205			`------------------------------------------------------------------------------`
206			`component sync_block --ok`
207			`port (`
208			`clk : in std_logic;`
209			`data_in : in std_logic;`
210			`data_out : out std_logic`
211			`);`
212			`end component;`
213
214
215
216			`------------------------------------------------------------------------------`
217			`-- Component declaration for the reset synchroniser`
218			`------------------------------------------------------------------------------`
219			`component reset_sync --ok`
220			`port (`
221			`reset_in : in std_logic; -- Active high asynchronous reset`
222			`enable : in std_logic;`
223			`clk : in std_logic; -- clock to be sync'ed to`
224			`reset_out : out std_logic -- "Synchronised" reset signal`
225			`);`
226			`end component;`
227
228
229			`------------------------------------------------------------------------------`
230			`-- Constants used in this top level wrapper.`
231			`------------------------------------------------------------------------------`
232			`constant BOARD_PHY_ADDR : std_logic_vector(7 downto 0) := "00000111";`
233
234
235			`------------------------------------------------------------------------------`
236			`-- internal signals used in this top level wrapper.`
237			`------------------------------------------------------------------------------`
238
239			`-- example design clocks`
240			`signal gtx_clk_bufg : std_logic;`
241			`signal refclk_bufg : std_logic;`
242			`signal rx_mac_aclk : std_logic;`
243
244			`-- tx handshaking`
245			`signal mac_tx_tready_int : std_logic;`
246			`signal tx_full_reg : std_logic;`
247			`signal tx_full_val : std_logic;`
248			`signal tx_data_reg : std_logic_vector(7 downto 0);`
249			`signal tx_last_reg : std_logic;`
250			`signal set_tx_reg : std_logic;`
251
252
253			`signal phy_resetn_int : std_logic;`
254
255			`-- resets (and reset generation)`
256			`signal local_chk_reset : std_logic;`
257			`signal chk_reset_int : std_logic;`
258			`signal chk_pre_resetn : std_logic := '0';`
259			`signal chk_resetn : std_logic := '0';`
260			`signal dcm_locked : std_logic;`
261			`signal tx_fifo_resetn : std_logic;`
262			`signal rx_fifo_resetn : std_logic;`
263
264			`signal glbl_rst_int : std_logic;`
265			`signal phy_reset_count : unsigned(5 downto 0);`
266			`signal glbl_rst_intn : std_logic;`
267
268			`-- pipeline register for RX signals`
269			`signal rx_data_val : std_logic_vector(7 downto 0);`
270			`signal rx_tvalid_val : std_logic;`
271			`signal rx_tlast_val : std_logic;`
272			`signal rx_data_reg : std_logic_vector(7 downto 0);`
273			`signal rx_tvalid_reg : std_logic;`
274			`signal rx_tlast_reg : std_logic;`
275			`signal rx_fifo_clock : std_logic;`
276
277			`attribute keep : string;`
278			`attribute keep of gtx_clk_bufg : signal is "true";`
279			`attribute keep of refclk_bufg : signal is "true";`
280			`attribute keep of mac_tx_tready_int : signal is "true";`
281			`attribute keep of tx_full_reg : signal is "true";`
282
283
284			`------------------------------------------------------------------------------`
285			`-- Begin architecture`
286			`------------------------------------------------------------------------------`
287
288			`begin`
289
290			`combinatorial: process (`
291			`rx_data_reg, rx_tvalid_reg, rx_tlast_reg,`
292			`mac_tx_tvalid, mac_tx_tready_int, tx_full_reg, tx_full_val, set_tx_reg`
293			`)`
294			`begin`
295			`-- output followers`
296			`mac_rx_tdata <= rx_data_reg;`
297			`mac_rx_tvalid <= rx_tvalid_reg;`
298			`mac_rx_tlast <= rx_tlast_reg;`
299			`mac_tx_tready <= not (tx_full_reg and not mac_tx_tready_int); -- if not full, we are ready to accept`
300
301			`-- control defaults`
302			`tx_full_val <= tx_full_reg;`
303			`set_tx_reg <= '0';`
304
305			`-- tx handshaking logic`
306			`if mac_tx_tvalid = '1' then`
307			`tx_full_val <= '1';`
308			`set_tx_reg <= '1';`
309			`elsif mac_tx_tready_int = '1' then`
310			`tx_full_val <= '0';`
311			`end if;`
312
313			`end process;`
314
315			`sequential: process(gtx_clk_bufg)`
316			`begin`
317			`if rising_edge(gtx_clk_bufg) then`
318			`if chk_resetn = '0' then`
319			`-- reset state variables`
320			`rx_data_reg <= (others => '0');`
321			`rx_tvalid_reg <= '0';`
322			`rx_tlast_reg <= '0';`
323			`tx_full_reg <= '0';`
324			`tx_data_reg <= (others => '0');`
325			`tx_last_reg <= '0';`
326			`else`
327			`-- register rx data`
328			`rx_data_reg <= rx_data_val;`
329			`rx_tvalid_reg <= rx_tvalid_val;`
330			`rx_tlast_reg <= rx_tlast_val;`
331
332			`-- process tx tvalid and tready`
333			`tx_full_reg <= tx_full_val;`
334			`if set_tx_reg = '1' then`
335			`tx_data_reg <= mac_tx_tdata;`
336			`tx_last_reg <= mac_tx_tlast;`
337			`else`
338			`tx_data_reg <= tx_data_reg;`
339			`tx_last_reg <= tx_last_reg;`
340			`end if;`
341			`end if;`
342			`end if;`
343			`end process;`
344
345			`------------------------------------------------------------------------------`
346			`-- Instantiate the Tri-Mode EMAC Block wrapper`
347			`------------------------------------------------------------------------------`
348			`v6emac_fifo_block : v6_emac_v2_1_fifo_block --ok`
349			`port map(`
350
351			`gtx_clk => gtx_clk_bufg,`
352			`-- Receiver Statistics Interface`
353			`-----------------------------------------`
354			`rx_mac_aclk => open,`
355			`rx_reset => open,`
356			`rx_statistics_vector => open,`
357			`rx_statistics_valid => open,`
358
359			`-- Receiver (AXI-S) Interface`
360			`------------------------------------------`
361			`rx_fifo_clock => gtx_clk_bufg,`
362			`rx_fifo_resetn => chk_resetn,`
363			`rx_axis_fifo_tdata => rx_data_val,`
364			`rx_axis_fifo_tvalid => rx_tvalid_val,`
365			`rx_axis_fifo_tready => mac_rx_tready,`
366			`rx_axis_fifo_tlast => rx_tlast_val,`
367
368			`-- Transmitter Statistics Interface`
369			`--------------------------------------------`
370			`tx_mac_aclk => open,`
371			`tx_reset => open,`
372			`tx_ifg_delay => x"12",`
373			`tx_statistics_vector => open,`
374			`tx_statistics_valid => open,`
375
376			`-- Transmitter (AXI-S) Interface`
377			`---------------------------------------------`
378			`tx_fifo_clock => gtx_clk_bufg,`
379			`tx_fifo_resetn => chk_resetn,`
380			`tx_axis_fifo_tdata => tx_data_reg,`
381			`tx_axis_fifo_tvalid => tx_full_reg,`
382			`tx_axis_fifo_tready => mac_tx_tready_int,`
383			`tx_axis_fifo_tlast => tx_last_reg,`
384
385			`-- MAC Control Interface`
386			`--------------------------`
387			`pause_req => '0',`
388			`pause_val => x"0000",`
389
390			`-- Reference clock for IDELAYCTRL's`
391			`refclk => refclk_bufg,`
392
393			`-- GMII Interface`
394			`gmii_txd => gmii_txd,`
395			`gmii_tx_en => gmii_tx_en,`
396			`gmii_tx_er => gmii_tx_er,`
397			`gmii_tx_clk => gmii_tx_clk,`
398			`gmii_rxd => gmii_rxd,`
399			`gmii_rx_dv => gmii_rx_dv,`
400			`gmii_rx_er => gmii_rx_er,`
401			`gmii_rx_clk => gmii_rx_clk,`
402			`gmii_col => gmii_col,`
403			`gmii_crs => gmii_crs,`
404			`mii_tx_clk => mii_tx_clk,`
405
406			`-- Initial Unicast Address Value`
407			`unicast_address => x"FFFFFFFFFFFF",`
408
409
410			`-- asynchronous reset`
411			`glbl_rstn => chk_resetn,`
412			`rx_axi_rstn => '1',`
413			`tx_axi_rstn => '1'`
414
415			`);`
416
417
418			`------------------------------------------------------------------------------`
419			`-- Clock logic to generate required clocks from the 200MHz on board`
420			`-- if 125MHz is available directly this can be removed`
421			`------------------------------------------------------------------------------`
422			`clock_generator : clk_wiz_v2_1`
423			`port map (`
424			`-- Clock in ports`
425			`CLK_IN1_P => clk_in_p,`
426			`CLK_IN1_N => clk_in_n,`
427			`-- Clock out ports`
428			`CLK_OUT1 => gtx_clk_bufg,`
429			`CLK_OUT2 => open,`
430			`CLK_OUT3 => refclk_bufg,`
431			`-- Status and control signals`
432			`RESET => glbl_rst,`
433			`LOCKED => dcm_locked`
434			`);`
435
436			`-----------------`
437			`-- global reset`
438			`glbl_reset_gen : reset_sync`
439			`port map (`
440			`reset_in => glbl_rst,`
441			`enable => dcm_locked,`
442			`clk => gtx_clk_bufg,`
443			`reset_out => glbl_rst_int`
444			`);`
445
446			`glbl_rst_intn <= not glbl_rst_int;`
447
448			`-- generate the user side clocks`
449			`mac_tx_clock <= gtx_clk_bufg;`
450			`mac_rx_clock <= gtx_clk_bufg;`
451
452			`------------------------------------------------------------------------------`
453			`-- Generate resets`
454			`------------------------------------------------------------------------------`
455			`-- in each case the async reset is first captured and then synchronised`
456
457
458			`local_chk_reset <= glbl_rst or mac_reset;`
459
460			`-----------------`
461			`-- data check reset`
462			`chk_reset_gen : reset_sync`
463			`port map (`
464			`reset_in => local_chk_reset,`
465			`enable => dcm_locked,`
466			`clk => gtx_clk_bufg,`
467			`reset_out => chk_reset_int`
468			`);`
469
470			`-- Create fully synchronous reset in the gtx clock domain.`
471			`gen_chk_reset : process (gtx_clk_bufg)`
472			`begin`
473			`if gtx_clk_bufg'event and gtx_clk_bufg = '1' then`
474			`if chk_reset_int = '1' then`
475			`chk_pre_resetn <= '0';`
476			`chk_resetn <= '0';`
477			`else`
478			`chk_pre_resetn <= '1';`
479			`chk_resetn <= chk_pre_resetn;`
480			`end if;`
481			`end if;`
482			`end process gen_chk_reset;`
483
484
485
486			`-----------------`
487			`-- PHY reset`
488			`-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles`
489			`-- this is derived using the 125MHz available and a 6 bit counter`
490			`gen_phy_reset : process (gtx_clk_bufg)`
491			`begin`
492			`if gtx_clk_bufg'event and gtx_clk_bufg = '1' then`
493			`if glbl_rst_intn = '0' then`
494			`phy_resetn_int <= '0';`
495			`phy_reset_count <= (others => '0');`
496			`else`
497			`if phy_reset_count /= "111111" then`
498			`phy_reset_count <= phy_reset_count + "000001";`
499			`else`
500			`phy_resetn_int <= '1';`
501			`end if;`
502			`end if;`
503			`end if;`
504			`end process gen_phy_reset;`
505
506			`phy_resetn <= phy_resetn_int;`
507
508
509			`end wrapper;`