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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [arp_STORE_br.vhd] - Blame information for rev 36

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1 10 pjf
----------------------------------------------------------------------------------
2
-- Company: 
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-- Engineer:            Peter Fall
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-- 
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-- Create Date:    12:00:04 05/31/2011 
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-- Design Name: 
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-- Module Name:    arp_STORE_br - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
11
-- Description:
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--              ARP storage table using block ram with lookup based on IP address
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--              implements upto 255 entries with sequential search
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--              uses round robin overwrite when full (LRU would be better, but ...)
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--
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--              store may take a number of cycles and the request is latched
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--              lookup may take a number of cycles. Assumes that request signals remain valid during lookup
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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use ieee.std_logic_unsigned.all;
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use work.arp_types.all;
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32 18 pjf
entity arp_STORE_br is
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  generic (
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    MAX_ARP_ENTRIES : integer := 255          -- max entries in the store
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    );
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  port (
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    -- read signals
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    read_req    : in  arp_store_rdrequest_t;  -- requesting a lookup or store
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    read_result : out arp_store_result_t;     -- the result
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    -- write signals
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    write_req   : in  arp_store_wrrequest_t;  -- requesting a lookup or store
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    -- control and status signals
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    clear_store : in  std_logic;              -- erase all entries
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    entry_count : out unsigned(7 downto 0);   -- how many entries currently in store
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    -- system signals
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    clk         : in  std_logic;
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    reset       : in  std_logic
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    );
49 10 pjf
end arp_STORE_br;
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51
architecture Behavioral of arp_STORE_br is
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  type st_state_t is (IDLE, PAUSE, SEARCH, FOUND, NOT_FOUND);
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  type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0);
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  type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0);
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  subtype addr_t is integer range 0 to MAX_ARP_ENTRIES;
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59
  type count_mode_t is (RST, INCR, HOLD);
60
 
61
  type mode_t is (MREAD, MWRITE);
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63
  -- state variables
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  signal ip_ram          : ip_ram_t;     -- will be implemented as block ram
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  signal mac_ram         : mac_ram_t;    -- will be implemented as block ram     
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  signal st_state        : st_state_t;
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  signal next_write_addr : addr_t;       -- where to make the next write
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  signal num_entries     : addr_t;       -- number of entries in the store
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  signal next_read_addr  : addr_t;       -- next addr to read from
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  signal entry_found     : arp_entry_t;  -- entry found in search
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  signal mode            : mode_t;       -- are we writing or reading?
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  signal req_entry       : arp_entry_t;  -- entry latched from req
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74
  -- busses
75
  signal next_st_state          : st_state_t;
76
  signal arp_entry_val          : arp_entry_t;
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  signal mode_val               : mode_t;
78
  signal write_addr             : addr_t;        -- actual write address to use
79
  signal read_result_int        : arp_store_result_t;
80
 
81
  -- control signals
82
  signal set_st_state        : std_logic;
83
  signal set_next_write_addr : count_mode_t;
84
  signal set_num_entries     : count_mode_t;
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  signal set_next_read_addr  : count_mode_t;
86
  signal write_ram           : std_logic;
87
  signal set_entry_found     : std_logic;
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  signal set_mode            : std_logic;
89
 
90
  function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is
91
    variable ret : arp_store_rslt_t;
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  begin
93
    case status is
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      when IDLE =>
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        ret := status;
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      when others =>
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        if mode = MWRITE then
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          ret := BUSY;
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        else
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          ret := status;
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        end if;
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    end case;
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    return ret;
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  end read_status;
105
 
106 10 pjf
begin
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  combinatorial : process (
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    -- input signals
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    read_req, write_req, clear_store, reset,
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    -- state variables
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    st_state, next_write_addr, num_entries,
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    next_read_addr, entry_found, mode, req_entry,
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    -- busses
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    arp_entry_val
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    -- control signals
116
    )
117
  begin
118
    -- set output followers
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    read_result_int.status <= IDLE;
120
    read_result_int.entry  <= entry_found;
121
    entry_count        <= to_unsigned(num_entries, 8);
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123 18 pjf
    -- set bus defaults
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    next_st_state <= IDLE;
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    mode_val      <= MREAD;
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    write_addr    <= next_write_addr;
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128 18 pjf
    -- set signal defaults
129
    set_st_state        <= '0';
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    set_next_write_addr <= HOLD;
131
    set_num_entries     <= HOLD;
132
    set_next_read_addr  <= HOLD;
133
    write_ram           <= '0';
134
    set_entry_found     <= '0';
135
    set_mode            <= '0';
136
 
137
    -- STORE FSM
138
    case st_state is
139
      when IDLE =>
140
        if write_req.req = '1' then
141
                                        -- need to search to see if this IP already there
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          set_next_read_addr <= RST;    -- start lookup from beginning
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          mode_val           <= MWRITE;
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          set_mode           <= '1';
145
          next_st_state      <= PAUSE;
146
          set_st_state       <= '1';
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        elsif read_req.req = '1' then
148
          set_next_read_addr <= RST;    -- start lookup from beginning
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          mode_val           <= MREAD;
150
          set_mode           <= '1';
151
          next_st_state      <= PAUSE;
152
          set_st_state       <= '1';
153
        end if;
154
 
155
      when PAUSE =>
156
        -- wait until read addr is latched and we get first data out of the ram
157
        read_result_int.status <= read_status(BUSY, mode);
158
        set_next_read_addr <= INCR;
159
        next_st_state      <= SEARCH;
160
        set_st_state       <= '1';
161
 
162
      when SEARCH =>
163
        read_result_int.status                                    <= read_status(SEARCHING, mode);
164
        -- check if have a match at this entry
165
        if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
166
                                        -- found it
167
          set_entry_found <= '1';
168
          next_st_state   <= FOUND;
169
          set_st_state    <= '1';
170
        elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
171
                                        -- reached end of entry table
172
          read_result_int.status <= read_status(NOT_FOUND, mode);
173
          next_st_state      <= NOT_FOUND;
174
          set_st_state       <= '1';
175
        else
176
                                        -- no match at this entry , go to next
177
          set_next_read_addr <= INCR;
178
        end if;
179
 
180
      when FOUND =>
181
        read_result_int.status <= read_status(FOUND, mode);
182
        if mode = MWRITE then
183
          write_addr    <= next_read_addr - 1;
184
          write_ram     <= '1';
185
          next_st_state <= IDLE;
186
          set_st_state  <= '1';
187
        elsif read_req.req = '0' then   -- wait in this state until request de-asserted
188
          next_st_state <= IDLE;
189
          set_st_state  <= '1';
190
        end if;
191
 
192
      when NOT_FOUND =>
193
        read_result_int.status <= read_status(NOT_FOUND, mode);
194
        if mode = MWRITE then
195
                                        -- need to write into the next free slot
196
          write_addr          <= next_write_addr;
197
          write_ram           <= '1';
198
          set_next_write_addr <= INCR;
199
          if num_entries < MAX_ARP_ENTRIES then
200
                                        -- if not full, count another entry (if full, it just wraps)
201
            set_num_entries <= INCR;
202
          end if;
203
          next_st_state <= IDLE;
204
          set_st_state  <= '1';
205
        elsif read_req.req = '0' then   -- wait in this state until request de-asserted
206
          next_st_state <= IDLE;
207
          set_st_state  <= '1';
208
        end if;
209
 
210
    end case;
211
  end process;
212
 
213
  sequential : process (clk)
214
  begin
215
    if rising_edge(clk) then
216
      -- ram processing
217
      if write_ram = '1' then
218
        ip_ram(write_addr)  <= req_entry.ip;
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        mac_ram(write_addr) <= req_entry.mac;
220
      end if;
221
      if next_read_addr < MAX_ARP_ENTRIES then
222
        arp_entry_val.ip  <= ip_ram(next_read_addr);
223
        arp_entry_val.mac <= mac_ram(next_read_addr);
224
      else
225
        arp_entry_val.ip  <= (others => '0');
226
        arp_entry_val.mac <= (others => '0');
227
      end if;
228
 
229
      read_result <= read_result_int;
230
 
231
      if reset = '1' or clear_store = '1' then
232
        -- reset state variables
233
        st_state        <= IDLE;
234
        next_write_addr <= 0;
235
        num_entries     <= 0;
236
        next_read_addr  <= 0;
237
        entry_found.ip  <= (others => '0');
238
        entry_found.mac <= (others => '0');
239
        req_entry.ip    <= (others => '0');
240
        req_entry.mac   <= (others => '0');
241
        mode            <= MREAD;
242
 
243
      else
244
        -- Next req_state processing
245
        if set_st_state = '1' then
246
          st_state <= next_st_state;
247
        else
248
          st_state <= st_state;
249
        end if;
250
 
251
        -- mode setting and write request latching
252
        if set_mode = '1' then
253
          mode <= mode_val;
254
          if mode_val = MWRITE then
255
            req_entry <= write_req.entry;
256
          else
257
            req_entry.ip  <= read_req.ip;
258
            req_entry.mac <= (others => '0');
259
          end if;
260
        else
261
          mode      <= mode;
262
          req_entry <= req_entry;
263
        end if;
264
 
265
        -- latch entry found
266
        if set_entry_found = '1' then
267
          entry_found <= arp_entry_val;
268
        else
269
          entry_found <= entry_found;
270
        end if;
271
 
272
        -- next_write_addr counts and wraps
273
        case set_next_write_addr is
274
          when HOLD => next_write_addr                                             <= next_write_addr;
275
          when RST  => next_write_addr                                             <= 0;
276
          when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if;
277
        end case;
278
 
279
        -- num_entries counts and holds at max
280
        case set_num_entries is
281
          when HOLD => num_entries                                           <= num_entries;
282
          when RST  => num_entries                                           <= 0;
283
          when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if;
284
        end case;
285
 
286
        -- next_read_addr counts and wraps
287
        case set_next_read_addr is
288
          when HOLD => next_read_addr                                          <= next_read_addr;
289
          when RST  => next_read_addr                                          <= 0;
290
          when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if;
291
        end case;
292
 
293
      end if;
294
    end if;
295
  end process;
296
 
297 10 pjf
end Behavioral;

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