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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [arpv2.vhd] - Blame information for rev 18

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1 10 pjf
----------------------------------------------------------------------------------
2
-- Company: 
3 18 pjf
-- Engineer:            Peter Fall
4 10 pjf
-- 
5
-- Create Date:    12:00:04 05/31/2011 
6
-- Design Name: 
7
-- Module Name:    arpv2 - Structural 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description:
12 18 pjf
--              handle simple IP lookup in 1-deep cache and arp store
13
--              request cache fill through ARP protocol if required
14
--              Handle ARP protocol
15
--              Respond to ARP requests and replies
16
--              Ignore pkts that are not ARP
17
--              Ignore pkts that are not addressed to us
18 10 pjf
--
19 18 pjf
--              structural decomposition includes
20
--                      arp TX block            - encoding of ARP protocol
21
--                      arp RX block            - decoding of ARP protocol
22
--                      arp REQ block           - sequencing requests for resolution
23
--                      arp STORE block - storing address resolution entries (indexed by IP addr)
24
--                      arp sync block          - sync between master RX clock and TX clock domains
25
--
26 10 pjf
-- Dependencies: 
27
--
28
-- Revision: 
29 18 pjf
-- Revision 0.01 - File Created
30 10 pjf
-- Additional Comments: 
31
--
32
----------------------------------------------------------------------------------
33
library IEEE;
34 18 pjf
use IEEE.STD_LOGIC_1164.all;
35
use IEEE.NUMERIC_STD.all;
36 10 pjf
use work.arp_types.all;
37
 
38
entity arpv2 is
39 18 pjf
  generic (
40
    no_default_gateway : boolean := true;  -- set to false if communicating with devices accessed
41
                                            -- though a "default gateway or router"
42
    CLOCK_FREQ      : integer := 125000000;  -- freq of data_in_clk -- needed to timout cntr
43
    ARP_TIMEOUT     : integer := 60;    -- ARP response timeout (s)
44
    ARP_MAX_PKT_TMO : integer := 5;     -- # wrong nwk pkts received before set error
45
    MAX_ARP_ENTRIES : integer := 255    -- max entries in the arp store
46
    );
47
  port (
48
    -- lookup request signals
49
    arp_req_req     : in  arp_req_req_type;
50
    arp_req_rslt    : out arp_req_rslt_type;
51
    -- MAC layer RX signals
52
    data_in_clk     : in  std_logic;
53
    reset           : in  std_logic;
54
    data_in         : in  std_logic_vector (7 downto 0);  -- ethernet frame (from dst mac addr through to last byte of frame)
55
    data_in_valid   : in  std_logic;    -- indicates data_in valid on clock
56
    data_in_last    : in  std_logic;    -- indicates last data in frame
57
    -- MAC layer TX signals
58
    mac_tx_req      : out std_logic;  -- indicates that ip wants access to channel (stays up for as long as tx)
59
    mac_tx_granted  : in  std_logic;  -- indicates that access to channel has been granted            
60
    data_out_clk    : in  std_logic;
61
    data_out_ready  : in  std_logic;    -- indicates system ready to consume data
62
    data_out_valid  : out std_logic;    -- indicates data out is valid
63
    data_out_first  : out std_logic;  -- with data out valid indicates the first byte of a frame
64
    data_out_last   : out std_logic;  -- with data out valid indicates the last byte of a frame
65
    data_out        : out std_logic_vector (7 downto 0);  -- ethernet frame (from dst mac addr through to last byte of frame)
66
    -- system signals
67
    our_mac_address : in  std_logic_vector (47 downto 0);
68
    our_ip_address  : in  std_logic_vector (31 downto 0);
69
    nwk_gateway     : in  std_logic_vector (31 downto 0) := (others => '0');  -- IP address of default gateway
70
    nwk_mask        : in  std_logic_vector (31 downto 0) := (others => '0');  -- Net mask
71
    control         : in  arp_control_type;
72
    req_count       : out std_logic_vector(7 downto 0)    -- count of arp pkts received
73
    );
74 10 pjf
end arpv2;
75
 
76
architecture structural of arpv2 is
77
 
78 18 pjf
  component arp_req
79
    generic (
80
      no_default_gateway : boolean := true;
81
      CLOCK_FREQ      : integer := 125000000;  -- freq of data_in_clk -- needed to timout cntr
82
      ARP_TIMEOUT     : integer := 60;  -- ARP response timeout (s)
83
      ARP_MAX_PKT_TMO : integer := 5    -- # wrong nwk pkts received before set error
84
      );
85
    port (
86
      -- lookup request signals
87
      arp_req_req      : in  arp_req_req_type;   -- request for a translation from IP to MAC
88
      arp_req_rslt     : out arp_req_rslt_type;  -- the result
89
      -- external arp store signals
90
      arp_store_req    : out arp_store_rdrequest_t;          -- requesting a lookup or store
91
      arp_store_result : in  arp_store_result_t;             -- the result
92
      -- network request signals
93
      arp_nwk_req      : out arp_nwk_request_t;  -- requesting resolution via the network
94
      arp_nwk_result   : in  arp_nwk_result_t;   -- the result
95
      -- system signals
96
      clear_cache      : in  std_logic;          -- clear the internal cache
97
      nwk_gateway      : in  std_logic_vector(31 downto 0);  -- IP address of default gateway
98
      nwk_mask         : in  std_logic_vector(31 downto 0);  -- Net mask
99
      clk              : in  std_logic;
100
      reset            : in  std_logic
101
      );
102
  end component;
103 10 pjf
 
104 18 pjf
  component arp_tx
105
    port(
106
      -- control signals
107
      send_I_have     : in  std_logic;  -- pulse will be latched
108
      arp_entry       : in  arp_entry_t;  -- arp target for I_have req (will be latched)
109
      send_who_has    : in  std_logic;  -- pulse will be latched
110
      ip_entry        : in  std_logic_vector (31 downto 0);  -- ip target for who_has req (will be latched)
111
      -- MAC layer TX signals
112
      mac_tx_req      : out std_logic;  -- indicates that ip wants access to channel (stays up for as long as tx)
113
      mac_tx_granted  : in  std_logic;  -- indicates that access to channel has been granted            
114
      data_out_ready  : in  std_logic;  -- indicates system ready to consume data
115
      data_out_valid  : out std_logic;  -- indicates data out is valid
116
      data_out_first  : out std_logic;  -- with data out valid indicates the first byte of a frame
117
      data_out_last   : out std_logic;  -- with data out valid indicates the last byte of a frame
118
      data_out        : out std_logic_vector (7 downto 0);  -- ethernet frame (from dst mac addr through to last byte of frame)
119
      -- system signals
120
      our_mac_address : in  std_logic_vector (47 downto 0);
121
      our_ip_address  : in  std_logic_vector (31 downto 0);
122
      tx_clk          : in  std_logic;
123
      reset           : in  std_logic
124
      );
125
  end component;
126
 
127
  component arp_rx
128
    port(
129
      -- MAC layer RX signals
130
      data_in               : in  std_logic_vector (7 downto 0);  -- ethernet frame (from dst mac addr through to last byte of frame)
131
      data_in_valid         : in  std_logic;    -- indicates data_in valid on clock
132
      data_in_last          : in  std_logic;    -- indicates last data in frame
133
      -- ARP output signals
134
      recv_who_has          : out std_logic;    -- pulse will be latched
135
      arp_entry_for_who_has : out arp_entry_t;  -- target for who_has msg (Iie, who to reply to)
136
      recv_I_have           : out std_logic;    -- pulse will be latched
137
      arp_entry_for_I_have  : out arp_entry_t;  -- arp target for I_have msg
138
      -- control and status signals
139
      req_count             : out std_logic_vector(7 downto 0);   -- count of arp pkts received
140
      -- system signals
141
      our_ip_address        : in  std_logic_vector (31 downto 0);
142
      rx_clk                : in  std_logic;
143
      reset                 : in  std_logic
144
      );
145
  end component;
146
 
147
 
148
  component arp_store_br
149
    generic (
150
      MAX_ARP_ENTRIES : integer := 255          -- max entries in the store
151
      );
152
    port (
153
      -- read signals
154
      read_req    : in  arp_store_rdrequest_t;  -- requesting a lookup or store
155
      read_result : out arp_store_result_t;     -- the result
156
      -- write signals
157
      write_req   : in  arp_store_wrrequest_t;  -- requesting a lookup or store
158
      -- control and status signals
159
      clear_store : in  std_logic;              -- erase all entries
160
      entry_count : out unsigned(7 downto 0);   -- how many entries currently in store
161
      -- system signals
162
      clk         : in  std_logic;
163
      reset       : in  std_logic
164
      );
165
  end component;
166
 
167
  component arp_sync
168
    port (
169
      -- REQ to TX
170
      arp_nwk_req           : in  arp_nwk_request_t;  -- request for a translation from IP to MAC
171
      send_who_has          : out std_logic;
172
      ip_entry              : out std_logic_vector (31 downto 0);
173
      -- RX to TX
174
      recv_who_has          : in  std_logic;          -- this is for us, we will respond
175
      arp_entry_for_who_has : in  arp_entry_t;
176
      send_I_have           : out std_logic;
177
      arp_entry             : out arp_entry_t;
178
      -- RX to REQ
179
      I_have_received       : in  std_logic;
180
      nwk_result_status     : out arp_nwk_rslt_t;
181
      -- System Signals
182
      rx_clk                : in  std_logic;
183
      tx_clk                : in  std_logic;
184
      reset                 : in  std_logic
185
      );
186
  end component;
187
 
188
 
189
  -- interconnect REQ -> ARP_TX
190
  signal arp_nwk_req_int : arp_nwk_request_t;  -- tx req from REQ
191
 
192
  signal send_I_have_int  : std_logic;
193
  signal arp_entry_int    : arp_entry_t;
194
  signal send_who_has_int : std_logic;
195
  signal ip_entry_int     : std_logic_vector (31 downto 0);
196
 
197
  -- interconnect REQ <-> ARP_STORE
198
  signal arp_store_req_int    : arp_store_rdrequest_t;  -- lookup request
199
  signal arp_store_result_int : arp_store_result_t;     -- lookup result
200
 
201
  -- interconnect ARP_RX -> REQ
202
  signal nwk_result_status_int : arp_nwk_rslt_t;  -- response from a TX req
203
 
204
  -- interconnect ARP_RX -> ARP_STORE
205
  signal recv_I_have_int          : std_logic;  -- path to store new arp entry
206
  signal arp_entry_for_I_have_int : arp_entry_t;
207
 
208
  -- interconnect ARP_RX -> ARP_TX
209
  signal recv_who_has_int          : std_logic;    -- path for reply when we can anser
210
  signal arp_entry_for_who_has_int : arp_entry_t;  -- target for who_has msg (ie, who to reply to)
211
 
212
 
213
begin
214
 
215
 
216
  req : arp_req
217
    generic map (
218
      no_default_gateway => no_default_gateway,
219
      CLOCK_FREQ      => CLOCK_FREQ,
220
      ARP_TIMEOUT     => ARP_TIMEOUT,
221
      ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO
222
      )
223
    port map (
224
      -- lookup request signals
225
      arp_req_req           => arp_req_req,
226
      arp_req_rslt          => arp_req_rslt,
227
      -- external arp store signals
228
      arp_store_req         => arp_store_req_int,
229
      arp_store_result      => arp_store_result_int,
230
      -- network request signals
231
      arp_nwk_req           => arp_nwk_req_int,
232
      arp_nwk_result.status => nwk_result_status_int,
233
      arp_nwk_result.entry  => arp_entry_for_I_have_int,
234
      -- system signals
235
      clear_cache           => control.clear_cache,
236
      nwk_gateway           => nwk_gateway,
237
      nwk_mask              => nwk_mask,
238
      clk                   => data_in_clk,
239
      reset                 => reset
240
      );
241
 
242
  sync : arp_sync port map (
243
    -- REQ to TX
244
    arp_nwk_req           => arp_nwk_req_int,
245
    send_who_has          => send_who_has_int,
246
    ip_entry              => ip_entry_int,
247
    -- RX to TX
248
    recv_who_has          => recv_who_has_int,
249
    arp_entry_for_who_has => arp_entry_for_who_has_int,
250
    send_I_have           => send_I_have_int,
251
    arp_entry             => arp_entry_int,
252
    -- RX to REQ
253
    I_have_received       => recv_I_have_int,
254
    nwk_result_status     => nwk_result_status_int,
255
    -- system
256
    rx_clk                => data_in_clk,
257
    tx_clk                => data_out_clk,
258
    reset                 => reset
259
    );
260
 
261
  tx : arp_tx port map (
262
    -- control signals
263
    send_I_have     => send_I_have_int,
264
    arp_entry       => arp_entry_int,
265
    send_who_has    => send_who_has_int,
266
    ip_entry        => ip_entry_int,
267
    -- MAC layer TX signals
268
    mac_tx_req      => mac_tx_req,
269
    mac_tx_granted  => mac_tx_granted,
270
    data_out_ready  => data_out_ready,
271
    data_out_valid  => data_out_valid,
272
    data_out_first  => data_out_first,
273
    data_out_last   => data_out_last,
274
    data_out        => data_out,
275
    -- system signals
276
    our_ip_address  => our_ip_address,
277
    our_mac_address => our_mac_address,
278
    tx_clk          => data_out_clk,
279
    reset           => reset
280
    );
281
 
282
  rx : arp_rx port map (
283
    -- MAC layer RX signals
284
    data_in               => data_in,
285
    data_in_valid         => data_in_valid,
286
    data_in_last          => data_in_last,
287
    -- ARP output signals
288
    recv_who_has          => recv_who_has_int,
289
    arp_entry_for_who_has => arp_entry_for_who_has_int,
290
    recv_I_have           => recv_I_have_int,
291
    arp_entry_for_I_have  => arp_entry_for_I_have_int,
292
    -- control and status signals
293
    req_count             => req_count,
294
    -- system signals
295
    our_ip_address        => our_ip_address,
296
    rx_clk                => data_in_clk,
297
    reset                 => reset
298
    );
299
 
300
  store : arp_store_br
301
    generic map (
302
      MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
303
      )
304
    port map (
305
      -- read signals
306
      read_req        => arp_store_req_int,
307
      read_result     => arp_store_result_int,
308
      -- write signals
309
      write_req.req   => recv_I_have_int,
310
      write_req.entry => arp_entry_for_I_have_int,
311
      -- control and status signals
312
      clear_store     => control.clear_cache,
313
      entry_count     => open,
314
      -- system signals
315
      clk             => data_in_clk,
316
      reset           => reset
317
      );
318
 
319
 
320 10 pjf
end structural;
321
 

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