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##############################################################
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#
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# Xilinx Core Generator version 13.4
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# Date: Sat Apr 21 12:31:20 2012
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:v6_emac:2.2
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6vlx240t
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SET devicefamily = virtex6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ff1156
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SET removerpms = false
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SET simulationfiles = Structural
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SET speedgrade = -1
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT Virtex-6_Embedded_Tri-Mode_Ethernet_MAC_Wrapper family Xilinx,_Inc. 2.2
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# END Select
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# BEGIN Parameters
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CSET address_filter=false
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CSET address_filter_enable=false
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CSET axi_ipif=true
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CSET client_side_data_width=8_bit
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CSET clock_enable=true
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CSET component_name=mac_layer_v2_2
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CSET management_interface=false
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CSET mdio=false
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CSET number_of_address_table_entries=0
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CSET phy_an_enable=false
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CSET phy_ignore_adzero=false
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CSET phy_isolate=false
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CSET phy_link_timer_value=13D
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CSET phy_loopback_in_gtp=false
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CSET phy_loopback_msb=false
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CSET phy_powerdown=false
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CSET phy_reset=false
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CSET phy_unidirection_enable=false
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CSET physical_interface=GMII
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CSET rx_ctrl_lencheck_disable=false
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CSET rx_disable_length=false
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CSET rx_enable=true
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CSET rx_flow_control_enable=false
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CSET rx_half_duplex_enable=false
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CSET rx_in_band_fcs_enable=false
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CSET rx_jumbo_frame_enable=false
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CSET rx_reset=false
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CSET rx_vlan_enable=false
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CSET serial_mode_switch_enable=false
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CSET sgmii_mode=No_clock
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CSET speed=1000_Mbps
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CSET statistics_counters=false
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CSET statistics_reset=true
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CSET statistics_width=32bit
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CSET tx_enable=true
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CSET tx_flow_control_enable=false
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CSET tx_half_duplex_enable=false
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CSET tx_ifg_adjust_enable=false
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CSET tx_in_band_fcs_enable=false
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CSET tx_jumbo_frame_enable=false
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CSET tx_reset=false
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CSET tx_vlan_enable=false
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CSET unicast_pause_mac_address_1=AA
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CSET unicast_pause_mac_address_2=BB
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CSET unicast_pause_mac_address_3=CC
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CSET unicast_pause_mac_address_4=DD
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CSET unicast_pause_mac_address_5=EE
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CSET unicast_pause_mac_address_6=FF
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-01-07T15:29:19Z
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# END Extra information
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GENERATE
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# CRC: 107b69dd
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