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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [UDP_Complete.vhd] - Blame information for rev 10

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----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
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-- Create Date:    17:51:18 06/11/2011 
6
-- Design Name: 
7
-- Module Name:    UDP_Complete - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
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-- Tool versions: 
11
-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Revision 0.02 - separated RX and TX clocks
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
21
library IEEE;
22
use IEEE.STD_LOGIC_1164.ALL;
23
use IEEE.NUMERIC_STD.ALL;
24
use work.axi.all;
25
use work.ipv4_types.all;
26
use work.arp_types.all;
27
 
28
entity UDP_Complete is
29 8 pjf
         generic (
30
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
31 10 pjf
                        ARP_TIMEOUT                     : integer := 60;                                                                        -- ARP response timeout (s)
32
                        ARP_MAX_PKT_TMO : integer := 5;                                                                 -- # wrong nwk pkts received before set error
33
                        MAX_ARP_ENTRIES         : integer := 255                                                                        -- max entries in the ARP store
34 8 pjf
                        );
35 2 pjf
    Port (
36
                        -- UDP TX signals
37
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
38
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
39
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
40
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
41
                        -- UDP RX signals
42
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
43
                        udp_rxo                                 : out udp_rx_type;
44
                        -- IP RX signals
45
                        ip_rx_hdr                               : out ipv4_rx_header_type;
46
                        -- system signals
47
                        clk_in_p             : in  std_logic;                                           -- 200MHz clock input from board
48
                        clk_in_n             : in  std_logic;
49
                        clk_out                                 : out std_logic;
50
                        reset                                   : in  STD_LOGIC;
51
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
52
                        our_mac_address                 : in std_logic_vector (47 downto 0);
53 8 pjf
                        control                                 : in udp_control_type;
54 2 pjf
                        -- status signals
55
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
56
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
57
                        -- GMII Interface
58
                        phy_resetn           : out std_logic;
59
                        gmii_txd             : out std_logic_vector(7 downto 0);
60
                        gmii_tx_en           : out std_logic;
61
                        gmii_tx_er           : out std_logic;
62
                        gmii_tx_clk          : out std_logic;
63
                        gmii_rxd             : in  std_logic_vector(7 downto 0);
64
                        gmii_rx_dv           : in  std_logic;
65
                        gmii_rx_er           : in  std_logic;
66
                        gmii_rx_clk          : in  std_logic;
67
                        gmii_col             : in  std_logic;
68
                        gmii_crs             : in  std_logic;
69
                        mii_tx_clk           : in  std_logic
70
                        );
71
end UDP_Complete;
72
 
73 10 pjf
 
74
 
75
 
76 2 pjf
architecture structural of UDP_Complete is
77
 
78
  ------------------------------------------------------------------------------
79
  -- Component Declaration for UDP complete no mac
80
  ------------------------------------------------------------------------------
81
 
82
    COMPONENT UDP_Complete_nomac
83 8 pjf
         generic (
84
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
85 10 pjf
                        ARP_TIMEOUT                     : integer := 60;                                                                        -- ARP response timeout (s)
86
                        ARP_MAX_PKT_TMO : integer := 5;                                                                 -- # wrong nwk pkts received before set error
87
                        MAX_ARP_ENTRIES         : integer := 255                                                                        -- max entries in the ARP store
88 8 pjf
                        );
89
    Port (
90 2 pjf
                        -- UDP TX signals
91
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
92
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
93
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
94
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
95
                        -- UDP RX signals
96
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
97
                        udp_rxo                                 : out udp_rx_type;
98
                        -- IP RX signals
99
                        ip_rx_hdr                               : out ipv4_rx_header_type;
100
                        -- system signals
101
                        rx_clk                                  : in  STD_LOGIC;
102
                        tx_clk                                  : in  STD_LOGIC;
103
                        reset                                   : in  STD_LOGIC;
104
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
105
                        our_mac_address                 : in std_logic_vector (47 downto 0);
106 8 pjf
                        control                                 : in udp_control_type;
107 2 pjf
                        -- status signals
108
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
109
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
110
                        -- MAC Transmitter
111
                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
112
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
113
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
114 4 pjf
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
115 2 pjf
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
116
                        -- MAC Receiver
117
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
118
                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
119
                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
120
                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
121
                        );
122
    END COMPONENT;
123
 
124
 
125
  ------------------------------------------------------------------------------
126
  -- Component Declaration for the MAC layer
127
  ------------------------------------------------------------------------------
128 10 pjf
component mac_v2_2
129
-- component xv6mac_straight
130 2 pjf
         port (
131
                        -- System controls
132
                        ------------------
133
                        glbl_rst                      : in  std_logic;                                  -- asynchronous reset
134
                        mac_reset                       : in  std_logic;                                                        -- reset mac layer
135
                        clk_in_p                                : in  std_logic;                                        -- 200MHz clock input from board
136
                        clk_in_n                                : in  std_logic;
137
 
138
                        -- MAC Transmitter (AXI-S) Interface
139
                        ---------------------------------------------
140
                        mac_tx_clock                            : out  std_logic;                                                       -- data sampled on rising edge
141
                        mac_tx_tdata                            : in  std_logic_vector(7 downto 0);      -- data byte to tx
142
                        mac_tx_tvalid                           : in  std_logic;                                                        -- tdata is valid
143
                        mac_tx_tready                           : out std_logic;                                                        -- mac is ready to accept data
144
                        mac_tx_tlast                            : in  std_logic;                                                        -- indicates last byte of frame
145
 
146
                        -- MAC Receiver (AXI-S) Interface
147
                        ------------------------------------------
148
                        mac_rx_clock                            : out  std_logic;                                                       -- data valid on rising edge
149
                        mac_rx_tdata                            : out std_logic_vector(7 downto 0);      -- data byte received
150
                        mac_rx_tvalid                           : out std_logic;                                                        -- indicates tdata is valid
151
                        mac_rx_tready                           : in  std_logic;                                                        -- tells mac that we are ready to take data
152
                        mac_rx_tlast                            : out std_logic;                                                        -- indicates last byte of the trame
153
 
154
                        -- GMII Interface
155
                        -----------------     
156
                        phy_resetn                              : out std_logic;
157
                        gmii_txd                      : out std_logic_vector(7 downto 0);
158
                        gmii_tx_en                    : out std_logic;
159
                        gmii_tx_er                    : out std_logic;
160
                        gmii_tx_clk                   : out std_logic;
161
                        gmii_rxd                      : in  std_logic_vector(7 downto 0);
162
                        gmii_rx_dv                    : in  std_logic;
163
                        gmii_rx_er                    : in  std_logic;
164
                        gmii_rx_clk                   : in  std_logic;
165
                        gmii_col                      : in  std_logic;
166
                        gmii_crs                      : in  std_logic;
167
                        mii_tx_clk                    : in  std_logic
168
         );
169
end component;
170
 
171
 
172
        ---------------------------
173
        -- Signals
174
        ---------------------------
175
 
176
        -- MAC RX bus
177
        signal mac_rx_clock                     : std_logic;
178
        signal mac_rx_tdata                     : std_logic_vector (7 downto 0);
179
        signal mac_rx_tvalid                    : std_logic;
180
        signal mac_rx_tready                    : std_logic;
181
        signal mac_rx_tlast                     : std_logic;
182
        -- MAC TX bus
183
        signal mac_tx_clock                     : std_logic;
184
        signal mac_tx_tdata                     : std_logic_vector (7 downto 0);
185
        signal mac_tx_tvalid                    : std_logic;
186
        signal mac_tx_tready                    : std_logic;
187
        signal mac_tx_tlast                     : std_logic;
188
        -- control signals
189
        signal mac_tx_tready_int        : std_logic;
190
        signal mac_tx_granted_int       : std_logic;
191
 
192
 
193
begin
194
 
195
 
196
        process (mac_tx_clock)
197
        begin
198
                -- output followers
199
                clk_out <= mac_tx_clock;
200
        end process;
201
 
202
   ------------------------------------------------------------------------------
203
   -- Instantiate the UDP layer
204
   ------------------------------------------------------------------------------
205
 
206 8 pjf
   udp_block: UDP_Complete_nomac
207 10 pjf
                        generic map (
208 8 pjf
                         CLOCK_FREQ                     => CLOCK_FREQ,
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                         ARP_TIMEOUT            => ARP_TIMEOUT,
210
                         ARP_MAX_PKT_TMO        => ARP_MAX_PKT_TMO,
211
                         MAX_ARP_ENTRIES        => MAX_ARP_ENTRIES
212 8 pjf
                         )
213 10 pjf
                        PORT MAP (
214 2 pjf
                         -- UDP TX signals
215
          udp_tx_start                  => udp_tx_start,
216
          udp_txi                               => udp_txi,
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          udp_tx_result                 => udp_tx_result,
218
          udp_tx_data_out_ready => udp_tx_data_out_ready,
219
                         -- UDP RX signals
220
          udp_rx_start                  => udp_rx_start,
221
          udp_rxo                               => udp_rxo,
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                         -- IP RX signals
223
          ip_rx_hdr                             => ip_rx_hdr,
224
                         -- system signals
225
          rx_clk                                        => mac_rx_clock,
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          tx_clk                                        => mac_tx_clock,
227
          reset                                         => reset,
228
          our_ip_address                => our_ip_address,
229
          our_mac_address               => our_mac_address,
230
                         -- status signals
231
          arp_pkt_count                 => arp_pkt_count,
232
          ip_pkt_count                  => ip_pkt_count,
233 8 pjf
                         control                                        => control,
234 2 pjf
                         -- MAC Transmitter
235
          mac_tx_tready                 => mac_tx_tready_int,
236
          mac_tx_tvalid                 => mac_tx_tvalid,
237 4 pjf
                         mac_tx_tfirst                  => open,
238 2 pjf
          mac_tx_tlast                  => mac_tx_tlast,
239
          mac_tx_tdata                  => mac_tx_tdata,
240
                    -- MAC Receiver
241
          mac_rx_tdata                  => mac_rx_tdata,
242
          mac_rx_tvalid                 => mac_rx_tvalid,
243
                         mac_rx_tready                  => mac_rx_tready,
244
          mac_rx_tlast                  => mac_rx_tlast
245
        );
246
 
247
 
248
   ------------------------------------------------------------------------------
249
   -- Instantiate the MAC layer
250
   ------------------------------------------------------------------------------
251 10 pjf
        mac_block : mac_v2_2
252
--      mac_block : xv6mac_straight
253 2 pjf
                 Port map(
254
                                -- System controls
255
                                ------------------
256
                                glbl_rst                                => reset,
257
                                mac_reset         => '0',
258
                                clk_in_p          => clk_in_p,
259
                                clk_in_n          => clk_in_n,
260
 
261
                                -- MAC Transmitter (AXI-S) Interface
262
                                ---------------------------------------------
263
                                mac_tx_clock      => mac_tx_clock,
264
                                mac_tx_tdata      => mac_tx_tdata,
265
                                mac_tx_tvalid     => mac_tx_tvalid,
266
                                mac_tx_tready     => mac_tx_tready_int,
267
                                mac_tx_tlast      => mac_tx_tlast,
268
 
269
                                -- MAC Receiver (AXI-S) Interface
270
                                ------------------------------------------
271
                                mac_rx_clock      => mac_rx_clock,
272
                                mac_rx_tdata      => mac_rx_tdata,
273
                                mac_rx_tvalid     => mac_rx_tvalid,
274
                                mac_rx_tready     => mac_rx_tready,
275
                                mac_rx_tlast      => mac_rx_tlast,
276
 
277
                                -- GMII Interface
278
                                -----------------     
279
                                phy_resetn        => phy_resetn,
280
                                gmii_txd                => gmii_txd,
281
                                gmii_tx_en        => gmii_tx_en,
282
                                gmii_tx_er        => gmii_tx_er,
283
                                gmii_tx_clk       => gmii_tx_clk,
284
                                gmii_rxd                => gmii_rxd,
285
                                gmii_rx_dv        => gmii_rx_dv,
286
                                gmii_rx_er        => gmii_rx_er,
287
                                gmii_rx_clk       => gmii_rx_clk,
288
                                gmii_col        => gmii_col,
289
                                gmii_crs                => gmii_crs,
290
                                mii_tx_clk        => mii_tx_clk
291
                          );
292
 
293
 
294
end structural;
295
 
296 10 pjf
 

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