OpenCores
URL https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk

Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [UDP_Complete.vhd] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 pjf
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Create Date:    17:51:18 06/11/2011 
6
-- Design Name: 
7
-- Module Name:    UDP_Complete - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
13
-- Dependencies: 
14
--
15
-- Revision: 
16
-- Revision 0.01 - File Created
17
-- Revision 0.02 - separated RX and TX clocks
18
-- Additional Comments: 
19
--
20
----------------------------------------------------------------------------------
21
library IEEE;
22
use IEEE.STD_LOGIC_1164.ALL;
23
use IEEE.NUMERIC_STD.ALL;
24
use work.axi.all;
25
use work.ipv4_types.all;
26
use work.arp_types.all;
27
 
28
entity UDP_Complete is
29 8 pjf
         generic (
30
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
31
                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
32
                        );
33 2 pjf
    Port (
34
                        -- UDP TX signals
35
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
36
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
37
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
38
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
39
                        -- UDP RX signals
40
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
41
                        udp_rxo                                 : out udp_rx_type;
42
                        -- IP RX signals
43
                        ip_rx_hdr                               : out ipv4_rx_header_type;
44
                        -- system signals
45
                        clk_in_p             : in  std_logic;                                           -- 200MHz clock input from board
46
                        clk_in_n             : in  std_logic;
47
                        clk_out                                 : out std_logic;
48
                        reset                                   : in  STD_LOGIC;
49
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
50
                        our_mac_address                 : in std_logic_vector (47 downto 0);
51 8 pjf
                        control                                 : in udp_control_type;
52 2 pjf
                        -- status signals
53
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
54
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
55
                        -- GMII Interface
56
                        phy_resetn           : out std_logic;
57
                        gmii_txd             : out std_logic_vector(7 downto 0);
58
                        gmii_tx_en           : out std_logic;
59
                        gmii_tx_er           : out std_logic;
60
                        gmii_tx_clk          : out std_logic;
61
                        gmii_rxd             : in  std_logic_vector(7 downto 0);
62
                        gmii_rx_dv           : in  std_logic;
63
                        gmii_rx_er           : in  std_logic;
64
                        gmii_rx_clk          : in  std_logic;
65
                        gmii_col             : in  std_logic;
66
                        gmii_crs             : in  std_logic;
67
                        mii_tx_clk           : in  std_logic
68
                        );
69
end UDP_Complete;
70
 
71
architecture structural of UDP_Complete is
72
 
73
  ------------------------------------------------------------------------------
74
  -- Component Declaration for UDP complete no mac
75
  ------------------------------------------------------------------------------
76
 
77
    COMPONENT UDP_Complete_nomac
78 8 pjf
         generic (
79
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
80
                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
81
                        );
82
    Port (
83 2 pjf
                        -- UDP TX signals
84
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
85
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
86
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
87
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
88
                        -- UDP RX signals
89
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
90
                        udp_rxo                                 : out udp_rx_type;
91
                        -- IP RX signals
92
                        ip_rx_hdr                               : out ipv4_rx_header_type;
93
                        -- system signals
94
                        rx_clk                                  : in  STD_LOGIC;
95
                        tx_clk                                  : in  STD_LOGIC;
96
                        reset                                   : in  STD_LOGIC;
97
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
98
                        our_mac_address                 : in std_logic_vector (47 downto 0);
99 8 pjf
                        control                                 : in udp_control_type;
100 2 pjf
                        -- status signals
101
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
102
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
103
                        -- MAC Transmitter
104
                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
105
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
106
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
107 4 pjf
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
108 2 pjf
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
109
                        -- MAC Receiver
110
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
111
                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
112
                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
113
                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
114
                        );
115
    END COMPONENT;
116
 
117
 
118
  ------------------------------------------------------------------------------
119
  -- Component Declaration for the MAC layer
120
  ------------------------------------------------------------------------------
121
component mac_layer
122
         port (
123
                        -- System controls
124
                        ------------------
125
                        glbl_rst                      : in  std_logic;                                  -- asynchronous reset
126
                        mac_reset                       : in  std_logic;                                                        -- reset mac layer
127
                        clk_in_p                                : in  std_logic;                                        -- 200MHz clock input from board
128
                        clk_in_n                                : in  std_logic;
129
 
130
                        -- MAC Transmitter (AXI-S) Interface
131
                        ---------------------------------------------
132
                        mac_tx_clock                            : out  std_logic;                                                       -- data sampled on rising edge
133
                        mac_tx_tdata                            : in  std_logic_vector(7 downto 0);      -- data byte to tx
134
                        mac_tx_tvalid                           : in  std_logic;                                                        -- tdata is valid
135
                        mac_tx_tready                           : out std_logic;                                                        -- mac is ready to accept data
136
                        mac_tx_tlast                            : in  std_logic;                                                        -- indicates last byte of frame
137
 
138
                        -- MAC Receiver (AXI-S) Interface
139
                        ------------------------------------------
140
                        mac_rx_clock                            : out  std_logic;                                                       -- data valid on rising edge
141
                        mac_rx_tdata                            : out std_logic_vector(7 downto 0);      -- data byte received
142
                        mac_rx_tvalid                           : out std_logic;                                                        -- indicates tdata is valid
143
                        mac_rx_tready                           : in  std_logic;                                                        -- tells mac that we are ready to take data
144
                        mac_rx_tlast                            : out std_logic;                                                        -- indicates last byte of the trame
145
 
146
                        -- GMII Interface
147
                        -----------------     
148
                        phy_resetn                              : out std_logic;
149
                        gmii_txd                      : out std_logic_vector(7 downto 0);
150
                        gmii_tx_en                    : out std_logic;
151
                        gmii_tx_er                    : out std_logic;
152
                        gmii_tx_clk                   : out std_logic;
153
                        gmii_rxd                      : in  std_logic_vector(7 downto 0);
154
                        gmii_rx_dv                    : in  std_logic;
155
                        gmii_rx_er                    : in  std_logic;
156
                        gmii_rx_clk                   : in  std_logic;
157
                        gmii_col                      : in  std_logic;
158
                        gmii_crs                      : in  std_logic;
159
                        mii_tx_clk                    : in  std_logic
160
         );
161
end component;
162
 
163
 
164
        ---------------------------
165
        -- Signals
166
        ---------------------------
167
 
168
        -- MAC RX bus
169
        signal mac_rx_clock                     : std_logic;
170
        signal mac_rx_tdata                     : std_logic_vector (7 downto 0);
171
        signal mac_rx_tvalid                    : std_logic;
172
        signal mac_rx_tready                    : std_logic;
173
        signal mac_rx_tlast                     : std_logic;
174
        -- MAC TX bus
175
        signal mac_tx_clock                     : std_logic;
176
        signal mac_tx_tdata                     : std_logic_vector (7 downto 0);
177
        signal mac_tx_tvalid                    : std_logic;
178
        signal mac_tx_tready                    : std_logic;
179
        signal mac_tx_tlast                     : std_logic;
180
        -- control signals
181
        signal mac_tx_tready_int        : std_logic;
182
        signal mac_tx_granted_int       : std_logic;
183
 
184
 
185
begin
186
 
187
 
188
        process (mac_tx_clock)
189
        begin
190
                -- output followers
191
                clk_out <= mac_tx_clock;
192
        end process;
193
 
194
   ------------------------------------------------------------------------------
195
   -- Instantiate the UDP layer
196
   ------------------------------------------------------------------------------
197
 
198 8 pjf
   udp_block: UDP_Complete_nomac
199
                                generic map (
200
                         CLOCK_FREQ                     => CLOCK_FREQ,
201
                         ARP_TIMEOUT            => ARP_TIMEOUT
202
                         )
203
                        PORT MAP (
204 2 pjf
                         -- UDP TX signals
205
          udp_tx_start                  => udp_tx_start,
206
          udp_txi                               => udp_txi,
207
          udp_tx_result                 => udp_tx_result,
208
          udp_tx_data_out_ready => udp_tx_data_out_ready,
209
                         -- UDP RX signals
210
          udp_rx_start                  => udp_rx_start,
211
          udp_rxo                               => udp_rxo,
212
                         -- IP RX signals
213
          ip_rx_hdr                             => ip_rx_hdr,
214
                         -- system signals
215
          rx_clk                                        => mac_rx_clock,
216
          tx_clk                                        => mac_tx_clock,
217
          reset                                         => reset,
218
          our_ip_address                => our_ip_address,
219
          our_mac_address               => our_mac_address,
220
                         -- status signals
221
          arp_pkt_count                 => arp_pkt_count,
222
          ip_pkt_count                  => ip_pkt_count,
223 8 pjf
                         control                                        => control,
224 2 pjf
                         -- MAC Transmitter
225
          mac_tx_tready                 => mac_tx_tready_int,
226
          mac_tx_tvalid                 => mac_tx_tvalid,
227 4 pjf
                         mac_tx_tfirst                  => open,
228 2 pjf
          mac_tx_tlast                  => mac_tx_tlast,
229
          mac_tx_tdata                  => mac_tx_tdata,
230
                    -- MAC Receiver
231
          mac_rx_tdata                  => mac_rx_tdata,
232
          mac_rx_tvalid                 => mac_rx_tvalid,
233
                         mac_rx_tready                  => mac_rx_tready,
234
          mac_rx_tlast                  => mac_rx_tlast
235
        );
236
 
237
 
238
   ------------------------------------------------------------------------------
239
   -- Instantiate the MAC layer
240
   ------------------------------------------------------------------------------
241
        mac_block : mac_layer
242
                 Port map(
243
                                -- System controls
244
                                ------------------
245
                                glbl_rst                                => reset,
246
                                mac_reset         => '0',
247
                                clk_in_p          => clk_in_p,
248
                                clk_in_n          => clk_in_n,
249
 
250
                                -- MAC Transmitter (AXI-S) Interface
251
                                ---------------------------------------------
252
                                mac_tx_clock      => mac_tx_clock,
253
                                mac_tx_tdata      => mac_tx_tdata,
254
                                mac_tx_tvalid     => mac_tx_tvalid,
255
                                mac_tx_tready     => mac_tx_tready_int,
256
                                mac_tx_tlast      => mac_tx_tlast,
257
 
258
                                -- MAC Receiver (AXI-S) Interface
259
                                ------------------------------------------
260
                                mac_rx_clock      => mac_rx_clock,
261
                                mac_rx_tdata      => mac_rx_tdata,
262
                                mac_rx_tvalid     => mac_rx_tvalid,
263
                                mac_rx_tready     => mac_rx_tready,
264
                                mac_rx_tlast      => mac_rx_tlast,
265
 
266
                                -- GMII Interface
267
                                -----------------     
268
                                phy_resetn        => phy_resetn,
269
                                gmii_txd                => gmii_txd,
270
                                gmii_tx_en        => gmii_tx_en,
271
                                gmii_tx_er        => gmii_tx_er,
272
                                gmii_tx_clk       => gmii_tx_clk,
273
                                gmii_rxd                => gmii_rxd,
274
                                gmii_rx_dv        => gmii_rx_dv,
275
                                gmii_rx_er        => gmii_rx_er,
276
                                gmii_rx_clk       => gmii_rx_clk,
277
                                gmii_col        => gmii_col,
278
                                gmii_crs                => gmii_crs,
279
                                mii_tx_clk        => mii_tx_clk
280
                          );
281
 
282
 
283
end structural;
284
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.