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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [UDP_integration_example.vhd] - Blame information for rev 29

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1 2 pjf
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Create Date:    11:01:00 06/11/2011 
6
-- Design Name: 
7
-- Module Name:    UDP_integration_example - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
13
-- Dependencies: 
14
--
15
-- Revision: 
16
-- Revision 0.01 - File Created
17
-- Additional Comments: 
18
--
19
----------------------------------------------------------------------------------
20
library IEEE;
21
use IEEE.STD_LOGIC_1164.ALL;
22
use IEEE.NUMERIC_STD.ALL;
23
use work.axi.all;
24
use work.ipv4_types.all;
25
use work.arp_types.all;
26
 
27
entity UDP_integration_example is
28
    port (
29
                -- System signals
30
                ------------------
31
      reset                             : in  std_logic;                                        -- asynchronous reset
32
      clk_in_p                                  : in  std_logic;                                        -- 200MHz clock input from board
33
      clk_in_n                                  : in  std_logic;
34
 
35
                -- System controls
36
                ------------------
37
                PBTX                                                                    : in std_logic;
38 10 pjf
                PB_DO_SECOND_TX                                 : in std_logic;
39
                DO_SECOND_TX_LED                                        : out std_logic;
40 2 pjf
                UDP_RX                                                          : out std_logic;
41
                UDP_Start                                                       : out std_logic;
42
                PBTX_LED                                                                : out std_logic;
43
                TX_Started                                                      : out std_logic;
44
                TX_Completed                                            : out std_logic;
45 8 pjf
                TX_RSLT_0                                                       : out std_logic;
46
                TX_RSLT_1                                                       : out std_logic;
47 2 pjf
                reset_leds                                                      : in std_logic;
48
      display                           : out std_logic_vector(7 downto 0);
49
 
50
      -- GMII Interface
51
      -----------------     
52
      phy_resetn                                : out std_logic;
53
      gmii_txd                      : out std_logic_vector(7 downto 0);
54
      gmii_tx_en                    : out std_logic;
55
      gmii_tx_er                    : out std_logic;
56
      gmii_tx_clk                   : out std_logic;
57
      gmii_rxd                      : in  std_logic_vector(7 downto 0);
58
      gmii_rx_dv                    : in  std_logic;
59
      gmii_rx_er                    : in  std_logic;
60
      gmii_rx_clk                   : in  std_logic;
61
      gmii_col                      : in  std_logic;
62
      gmii_crs                      : in  std_logic;
63
      mii_tx_clk                    : in  std_logic
64
    );
65
end UDP_integration_example;
66
 
67
architecture Behavioral of UDP_integration_example is
68
 
69 10 pjf
 
70 2 pjf
  ------------------------------------------------------------------------------
71 10 pjf
  -- Component Declaration for the complete UDP layer
72 2 pjf
  ------------------------------------------------------------------------------
73
component UDP_Complete
74 8 pjf
         generic (
75
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
76 10 pjf
                        ARP_TIMEOUT                     : integer := 60;                                                                        -- ARP response timeout (s)
77
                        ARP_MAX_PKT_TMO : integer := 5;                                                                 -- # wrong nwk pkts received before set error
78
                        MAX_ARP_ENTRIES         : integer := 255                                                                        -- max entries in the ARP store
79 8 pjf
                        );
80 2 pjf
    Port (
81
                        -- UDP TX signals
82
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
83
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
84
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
85
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
86
                        -- UDP RX signals
87
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
88
                        udp_rxo                                 : out udp_rx_type;
89
                        -- IP RX signals
90
                        ip_rx_hdr                               : out ipv4_rx_header_type;
91
                        -- system signals
92
                        clk_in_p             : in  std_logic;                                           -- 200MHz clock input from board
93
                        clk_in_n             : in  std_logic;
94
                        clk_out                                 : out std_logic;
95
                        reset                                   : in  STD_LOGIC;
96
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
97
                        our_mac_address                 : in std_logic_vector (47 downto 0);
98 8 pjf
                        control                                 : in udp_control_type;
99 2 pjf
                        -- status signals
100
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
101
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
102
                        -- GMII Interface
103
                        phy_resetn           : out std_logic;
104
                        gmii_txd             : out std_logic_vector(7 downto 0);
105
                        gmii_tx_en           : out std_logic;
106
                        gmii_tx_er           : out std_logic;
107
                        gmii_tx_clk          : out std_logic;
108
                        gmii_rxd             : in  std_logic_vector(7 downto 0);
109
                        gmii_rx_dv           : in  std_logic;
110
                        gmii_rx_er           : in  std_logic;
111
                        gmii_rx_clk          : in  std_logic;
112
                        gmii_col             : in  std_logic;
113
                        gmii_crs             : in  std_logic;
114
                        mii_tx_clk           : in  std_logic
115
                        );
116
end component;
117
 
118 10 pjf
--      for UDP_block : UDP_Complete  use configuration work.UDP_Complete.udpc_multi_slot_arp;
119 2 pjf
 
120 10 pjf
 
121
        type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT, PAUSE, CHECK_SECOND_TX, SET_SEC_HDR);
122 2 pjf
        type count_mode_type is (RST, INCR, HOLD);
123
        type set_clr_type is (SET, CLR, HOLD);
124 10 pjf
        type sec_tx_ctrl_type is (CLR,PRIME,DO,HOLD);
125 2 pjf
 
126
        -- system signals
127
        signal clk_int                                                  : std_logic;
128
        signal our_mac                                          : STD_LOGIC_VECTOR (47 downto 0);
129
        signal our_ip                                                   : STD_LOGIC_VECTOR (31 downto 0);
130
        signal udp_tx_int                                               : udp_tx_type;
131
        signal udp_tx_result_int                        : std_logic_vector (1 downto 0);
132
        signal udp_tx_data_out_ready_int        : std_logic;
133
        signal udp_rx_int                                               : udp_rx_type;
134
        signal udp_tx_start_int                         : std_logic;
135
        signal udp_rx_start_int                         : std_logic;
136
        signal arp_pkt_count_int                        : STD_LOGIC_VECTOR(7 downto 0);
137
        signal ip_pkt_count_int                         : STD_LOGIC_VECTOR(7 downto 0);
138
        signal ip_rx_hdr_int                                    : ipv4_rx_header_type;
139
 
140
        -- state signals
141
        signal state                                                    : state_type;
142
        signal count                                                    : unsigned (7 downto 0);
143
        signal tx_hdr                                                   : udp_tx_header_type;
144
        signal tx_start_reg                                     : std_logic;
145
        signal tx_started_reg                           : std_logic;
146
        signal tx_fin_reg                                               : std_logic;
147 10 pjf
        signal prime_second_tx                          : std_logic; -- if want to do a 2nd tx after the first
148
        signal do_second_tx                                     : std_logic; -- if need to do a 2nd tx as next tx
149
 
150 2 pjf
        -- control signals
151
        signal next_state                                               : state_type;
152
        signal set_state                                                : std_logic;
153
        signal set_count                                                : count_mode_type;
154
        signal set_hdr                                                  : std_logic;
155
        signal set_tx_start                                     : set_clr_type;
156
        signal set_last                                         : std_logic;
157
        signal set_tx_started                           : set_clr_type;
158
        signal set_tx_fin                                               : set_clr_type;
159 6 pjf
        signal first_byte_rx                                    : STD_LOGIC_VECTOR(7 downto 0);
160 8 pjf
        signal control_int                                      : udp_control_type;
161 10 pjf
        signal set_second_tx                                    : sec_tx_ctrl_type;
162 8 pjf
 
163 2 pjf
begin
164
 
165
        process (
166 8 pjf
                our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
167 2 pjf
                udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
168 10 pjf
                reset, tx_started_reg, tx_fin_reg, tx_start_reg, state, prime_second_tx, do_second_tx, set_second_tx,
169
                PB_DO_SECOND_TX, do_second_tx
170 2 pjf
                )
171
        begin
172 8 pjf
                -- set up our local addresses and default controls
173 29 pjf
                our_ip  <= x"c0a80119";         -- 192.168.1.25
174 2 pjf
                our_mac         <= x"002320212223";
175 8 pjf
                control_int.ip_controls.arp_controls.clear_cache <= '0';
176 2 pjf
 
177
                -- determine RX good and error LEDs
178
                if udp_rx_int.hdr.is_valid = '1' then
179
                        UDP_RX <= '1';
180
                else
181
                        UDP_RX <= '0';
182
                end if;
183
 
184 8 pjf
                UDP_Start <= udp_rx_start_int;
185 2 pjf
                TX_Started <= tx_start_reg; --tx_started_reg;
186
                TX_Completed <= tx_fin_reg;
187 8 pjf
                TX_RSLT_0 <= udp_tx_result_int(0);
188
                TX_RSLT_1 <= udp_tx_result_int(1);
189 10 pjf
                DO_SECOND_TX_LED <= prime_second_tx;
190 2 pjf
 
191
                -- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
192
                display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
193 8 pjf
 
194
--              display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
195
                case state is
196
                        when IDLE                       => display (3 downto 0) <= "0001";
197
                        when WAIT_RX_DONE => display (3 downto 0) <= "0010";
198
                        when DATA_OUT           => display (3 downto 0) <= "0011";
199 10 pjf
                        when PAUSE                      => display (3 downto 0) <= "0100";
200
                        when CHECK_SECOND_TX    => display (3 downto 0) <= "0101";
201
                        when SET_SEC_HDR => display (3 downto 0) <= "0110";
202 8 pjf
                end case;
203
 
204 2 pjf
        end process;
205
 
206 8 pjf
        -- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
207 2 pjf
 
208 8 pjf
                -- TX response process - COMB
209 2 pjf
   tx_proc_combinatorial: process(
210
                -- inputs
211 8 pjf
                udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
212 10 pjf
                udp_tx_int.data.data_out_valid, PBTX, PB_DO_SECOND_TX,
213 2 pjf
                -- state
214 10 pjf
                state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, prime_second_tx, do_second_tx,
215 2 pjf
                -- controls
216
                next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
217 10 pjf
                set_tx_started, set_tx_fin, first_byte_rx, set_second_tx
218 2 pjf
                )
219
   begin
220
                -- set output_followers
221
                udp_tx_int.hdr <= tx_hdr;
222
                udp_tx_int.data.data_out_last <= set_last;
223
                udp_tx_start_int <= tx_start_reg;
224
 
225
                -- set control signal defaults
226
                next_state <= IDLE;
227
                set_state <= '0';
228
                set_count <= HOLD;
229
                set_hdr <= '0';
230
                set_tx_start <= HOLD;
231
                set_last <= '0';
232
                set_tx_started <= HOLD;
233
                set_tx_fin <= HOLD;
234 6 pjf
                first_byte_rx <= (others => '0');
235 8 pjf
                udp_tx_int.data.data_out <= (others => '0');
236
                udp_tx_int.data.data_out_valid <= '0';
237 10 pjf
                set_second_tx <= HOLD;
238 2 pjf
 
239 10 pjf
                if PB_DO_SECOND_TX = '1' then
240
                        set_second_tx <= PRIME;
241
                end if;
242
 
243 2 pjf
                -- FSM
244
                case state is
245
 
246
                        when IDLE =>
247
                                udp_tx_int.data.data_out_valid <= '0';
248
                                if udp_rx_start_int = '1' or PBTX = '1' then
249 6 pjf
                                        if udp_rx_start_int = '1' then
250
                                                first_byte_rx <= udp_rx_int.data.data_in;
251
                                        else
252
                                                first_byte_rx <= x"00";
253
                                        end if;
254 8 pjf
                                        set_tx_fin <= CLR;
255
                                        set_count <= RST;
256
                                        set_hdr <= '1';
257
                                        if udp_rx_int.data.data_in_last = '1' then
258
                                                set_tx_started <= SET;
259
                                                set_tx_start <= SET;
260
                                                next_state <= DATA_OUT;
261
                                                set_state <= '1';
262
                                        else
263
                                                next_state <= WAIT_RX_DONE;
264
                                                set_state <= '1';
265
                                        end if;
266
                                end if;
267
 
268
                        when WAIT_RX_DONE =>
269
                                -- wait until RX pkt fully received
270
                                if udp_rx_int.data.data_in_last = '1' then
271 2 pjf
                                        set_tx_started <= SET;
272
                                        set_tx_start <= SET;
273
                                        next_state <= DATA_OUT;
274
                                        set_state <= '1';
275
                                end if;
276 8 pjf
 
277 2 pjf
                        when DATA_OUT =>
278 8 pjf
                                if udp_tx_result_int = UDPTX_RESULT_ERR then
279
                                        -- have an error from the IP TX layer, clear down the TX
280
                                        set_tx_start <= CLR;
281
                                        set_tx_fin <= SET;
282
                                        set_tx_started <= CLR;
283 10 pjf
                                        set_second_tx <= CLR;
284 8 pjf
                                        next_state <= IDLE;
285
                                        set_state <= '1';
286
                                else
287
                                        if udp_tx_result_int = UDPTX_RESULT_SENDING then
288
                                                set_tx_start <= CLR;            -- reset out start req as soon as we know we are sending
289
                                        end if;
290
                                        if ip_rx_hdr_int.is_broadcast = '1' then
291
                                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";
292 2 pjf
                                        else
293 8 pjf
                                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
294 2 pjf
                                        end if;
295 8 pjf
                                        udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
296
                                        if udp_tx_data_out_ready_int = '1' then
297
                                                if unsigned(count) = x"03" then
298
                                                        set_last <= '1';
299
                                                        set_tx_fin <= SET;
300
                                                        set_tx_started <= CLR;
301 10 pjf
                                                        next_state <= PAUSE;
302 8 pjf
                                                        set_state <= '1';
303
                                                else
304
                                                        set_count <= INCR;
305
                                                end if;
306
                                        end if;
307 2 pjf
                                end if;
308 10 pjf
 
309
                        when PAUSE =>
310
                                next_state <= CHECK_SECOND_TX;
311
                                set_state <= '1';
312
 
313
 
314
                        when CHECK_SECOND_TX =>
315
                                if prime_second_tx = '1' then
316
                                        set_second_tx <= DO;
317
                                        next_state <= SET_SEC_HDR;
318
                                        set_state <= '1';
319
                                else
320
                                        set_second_tx <= CLR;
321
                                        next_state <= IDLE;
322
                                        set_state <= '1';
323
                                end if;
324 2 pjf
 
325 10 pjf
                        when SET_SEC_HDR =>
326
                                set_hdr <= '1';
327
                                        set_tx_started <= SET;
328
                                        set_tx_start <= SET;
329
                                        next_state <= DATA_OUT;
330
                                        set_state <= '1';
331
 
332 2 pjf
                end case;
333
        end process;
334
 
335
 
336
 
337
   -- TX response process - SEQ
338
   tx_proc_sequential: process(clk_int)
339
   begin
340
                if rising_edge(clk_int) then
341
                        if reset = '1' then
342
                                -- reset state variables
343
                                state <= IDLE;
344
                                count <= x"00";
345
                                tx_start_reg <= '0';
346
                                tx_hdr.dst_ip_addr <= (others => '0');
347
                                tx_hdr.dst_port <= (others => '0');
348
                                tx_hdr.src_port <= (others => '0');
349
                                tx_hdr.data_length <= (others => '0');
350
                                tx_hdr.checksum <= (others => '0');
351
                                tx_started_reg <= '0';
352
                                tx_fin_reg <= '0';
353
                                PBTX_LED <= '0';
354 10 pjf
                                do_second_tx <= '0';
355
                                prime_second_tx <= '0';
356 2 pjf
                        else
357
                                PBTX_LED <= PBTX;
358
 
359
                                -- Next rx_state processing
360
                                if set_state = '1' then
361
                                        state <= next_state;
362
                                else
363
                                        state <= state;
364
                                end if;
365
 
366
                                -- count processing
367
                                case set_count is
368
                                        when RST =>             count <= x"00";
369
                                        when INCR =>            count <= count + 1;
370
                                        when HOLD =>            count <= count;
371
                                end case;
372
 
373
                                -- set tx hdr
374
                                if set_hdr = '1' then
375 10 pjf
                                        -- select the dst addr of the tx:
376
                                        -- if do_second_tx, to solaris box
377
                                        -- otherwise control according to first byte of received data:
378
                                        --   B = broadcast
379
                                        --   C = to dummy address to test timeout
380
                                        --   D to solaris box
381
                                        --   otherwise, direct to sender
382
                                        if do_second_tx = '1' then
383
                                                tx_hdr.dst_ip_addr <= x"c0a80005";      -- set dst to solaris box at 192.168.0.5
384
                                        elsif first_byte_rx = x"42" then
385 8 pjf
                                                tx_hdr.dst_ip_addr <= IP_BC_ADDR;       -- send to Broadcast addr
386
                                        elsif first_byte_rx = x"43" then
387
                                                tx_hdr.dst_ip_addr <= x"c0bbccdd";      -- set dst unknown so get ARP timeout
388 10 pjf
                                        elsif first_byte_rx = x"44" then
389
                                                tx_hdr.dst_ip_addr <= x"c0a80005";      -- set dst to solaris box at 192.168.0.5
390 6 pjf
                                        else
391 8 pjf
                                                tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;       -- reply to sender
392 6 pjf
                                        end if;
393 2 pjf
                                        tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
394
                                        tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
395
                                        tx_hdr.data_length <= x"0004";
396
                                        tx_hdr.checksum <= x"0000";
397
                                else
398
                                        tx_hdr <= tx_hdr;
399
                                end if;
400
 
401
                                -- set tx start signal
402
                                case set_tx_start is
403
                                        when SET  => tx_start_reg <= '1';
404
                                        when CLR  => tx_start_reg <= '0';
405
                                        when HOLD => tx_start_reg <= tx_start_reg;
406
                                end case;
407
 
408
                                -- set tx started signal
409
                                case set_tx_started is
410
                                        when SET  => tx_started_reg <= '1';
411
                                        when CLR  => tx_started_reg <= '0';
412
                                        when HOLD => tx_started_reg <= tx_started_reg;
413
                                end case;
414
 
415
                                -- set tx finished signal
416
                                case set_tx_fin is
417
                                        when SET  => tx_fin_reg <= '1';
418
                                        when CLR  => tx_fin_reg <= '0';
419
                                        when HOLD => tx_fin_reg <= tx_fin_reg;
420
                                end case;
421 10 pjf
 
422
                                -- set do_second_tx
423
                                case set_second_tx is
424
                                        when PRIME  =>
425
                                                prime_second_tx <= '1';
426
                                        when DO =>
427
                                                prime_second_tx <= '0';
428
                                                do_second_tx <= '1';
429
                                        when CLR  =>
430
                                                prime_second_tx <= '0';
431
                                                do_second_tx <= '0';
432
                                        when HOLD =>
433
                                                prime_second_tx <= prime_second_tx;
434
                                                do_second_tx <= do_second_tx;
435
                                end case;
436 2 pjf
 
437
                        end if;
438
                end if;
439
 
440
        end process;
441 8 pjf
 
442 2 pjf
 
443
 
444
   ------------------------------------------------------------------------------
445
   -- Instantiate the UDP layer
446
   ------------------------------------------------------------------------------
447 8 pjf
    UDP_block : UDP_Complete
448
                generic map (
449 10 pjf
                                ARP_TIMEOUT             => 10           -- timeout in seconds
450 8 pjf
                         )
451
                PORT MAP (
452 2 pjf
                                -- UDP interface
453
                                udp_tx_start                    => udp_tx_start_int,
454
                                udp_txi                                         => udp_tx_int,
455
                                udp_tx_result                   => udp_tx_result_int,
456
                                udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
457
                                udp_rx_start                    => udp_rx_start_int,
458
                                udp_rxo                                         => udp_rx_int,
459
                                -- IP RX signals
460
                                ip_rx_hdr                               => ip_rx_hdr_int,
461
                                -- System interface
462
                                clk_in_p             => clk_in_p,
463
                                clk_in_n             => clk_in_n,
464
                                clk_out                                 => clk_int,
465
                                reset                                   => reset,
466
                                our_ip_address          => our_ip,
467
                                our_mac_address                 => our_mac,
468 8 pjf
                                control                                 => control_int,
469 2 pjf
                                -- status signals
470
                                arp_pkt_count                   => arp_pkt_count_int,
471
                                ip_pkt_count                    => ip_pkt_count_int,
472
                                -- GMII Interface
473
                                -----------------     
474
                                phy_resetn        => phy_resetn,
475
                                gmii_txd                => gmii_txd,
476
                                gmii_tx_en        => gmii_tx_en,
477
                                gmii_tx_er        => gmii_tx_er,
478
                                gmii_tx_clk       => gmii_tx_clk,
479
                                gmii_rxd                => gmii_rxd,
480
                                gmii_rx_dv        => gmii_rx_dv,
481
                                gmii_rx_er        => gmii_rx_er,
482
                                gmii_rx_clk       => gmii_rx_clk,
483
                                gmii_col        => gmii_col,
484
                                gmii_crs                => gmii_crs,
485
                                mii_tx_clk        => mii_tx_clk
486
        );
487
 
488
 
489
end Behavioral;
490
 

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